Add support for ARM's Advanced SIMD (NEON) instruction set.

[oota-llvm.git] / test / CodeGen / ARM / neon_ld1.ll

diff --git a/test/CodeGen/ARM/neon_ld1.ll b/test/CodeGen/ARM/neon_ld1.ll
new file mode 100644 (file)
index 0000000..8901ba1
--- /dev/null
+++ b/test/CodeGen/ARM/neon_ld1.ll
@@ -0,0 +1,22 @@
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fldd | count 4
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fstd
+; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | grep fmrrd
+
+define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {
+entry:
+       %0 = load <4 x i16>* %a, align 8                ; <<4 x i16>> [#uses=1]
+       %1 = load <4 x i16>* %b, align 8                ; <<4 x i16>> [#uses=1]
+       %2 = add <4 x i16> %0, %1               ; <<4 x i16>> [#uses=1]
+       %3 = bitcast <4 x i16> %2 to <2 x i32>          ; <<2 x i32>> [#uses=1]
+       store <2 x i32> %3, <2 x i32>* %r, align 8
+       ret void
+}
+
+define <2 x i32> @t2(<4 x i16>* %a, <4 x i16>* %b) nounwind readonly {
+entry:
+       %0 = load <4 x i16>* %a, align 8                ; <<4 x i16>> [#uses=1]
+       %1 = load <4 x i16>* %b, align 8                ; <<4 x i16>> [#uses=1]
+       %2 = sub <4 x i16> %0, %1               ; <<4 x i16>> [#uses=1]
+       %3 = bitcast <4 x i16> %2 to <2 x i32>          ; <<2 x i32>> [#uses=1]
+       ret <2 x i32> %3
+}