DI: Require subprogram definitions to be distinct

[oota-llvm.git] / test / CodeGen / ARM / mulhi.ll

diff --git a/test/CodeGen/ARM/mulhi.ll b/test/CodeGen/ARM/mulhi.ll
index 9367258ef5526edd0a3bd55277f8923228ee654b..c66a804808fd845f971a3fb104d01bf6567ccc9d 100644 (file)
--- a/test/CodeGen/ARM/mulhi.ll
+++ b/test/CodeGen/ARM/mulhi.ll
@@ -1,23 +1,54 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm -mattr=+v6
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm -mattr=+v6 | \
-; RUN:   grep smmul | wc -l | grep 1
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | grep umull | wc -l | grep 1
-
-int %smulhi(int %x, int %y) {
-        %tmp = cast int %x to ulong             ; <ulong> [#uses=1]
-        %tmp1 = cast int %y to ulong            ; <ulong> [#uses=1]
-        %tmp2 = mul ulong %tmp1, %tmp           ; <ulong> [#uses=1]
-        %tmp3 = shr ulong %tmp2, ubyte 32               ; <ulong> [#uses=1]
-        %tmp3 = cast ulong %tmp3 to int         ; <int> [#uses=1]
-        ret int %tmp3
+; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s -check-prefix=V6
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=V4
+; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s -check-prefix=M3
+
+define i32 @smulhi(i32 %x, i32 %y) nounwind {
+; V6-LABEL: smulhi:
+; V6: smmul
+
+; V4-LABEL: smulhi:
+; V4: smull
+
+; M3-LABEL: smulhi:
+; M3: smull
+        %tmp = sext i32 %x to i64               ; <i64> [#uses=1]
+        %tmp1 = sext i32 %y to i64              ; <i64> [#uses=1]
+        %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
+        %tmp3 = lshr i64 %tmp2, 32              ; <i64> [#uses=1]
+        %tmp3.upgrd.1 = trunc i64 %tmp3 to i32          ; <i32> [#uses=1]
+        ret i32 %tmp3.upgrd.1
 }
 
-int %umulhi(uint %x, uint %y) {
-        %tmp = cast uint %x to ulong            ; <ulong> [#uses=1]
-        %tmp1 = cast uint %y to ulong           ; <ulong> [#uses=1]
-        %tmp2 = mul ulong %tmp1, %tmp           ; <ulong> [#uses=1]
-        %tmp3 = shr ulong %tmp2, ubyte 32               ; <ulong> [#uses=1]
-        %tmp3 = cast ulong %tmp3 to int         ; <int> [#uses=1]
-        ret int %tmp3
+define i32 @umulhi(i32 %x, i32 %y) nounwind {
+; V6-LABEL: umulhi:
+; V6: umull
+
+; V4-LABEL: umulhi:
+; V4: umull
+
+; M3-LABEL: umulhi:
+; M3: umull
+        %tmp = zext i32 %x to i64               ; <i64> [#uses=1]
+        %tmp1 = zext i32 %y to i64              ; <i64> [#uses=1]
+        %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
+        %tmp3 = lshr i64 %tmp2, 32              ; <i64> [#uses=1]
+        %tmp3.upgrd.2 = trunc i64 %tmp3 to i32          ; <i32> [#uses=1]
+        ret i32 %tmp3.upgrd.2
 }
 
+; rdar://r10152911
+define i32 @t3(i32 %a) nounwind {
+; V6-LABEL: t3:
+; V6: smmla
+
+; V4-LABEL: t3:
+; V4: smull
+
+; M3-LABEL: t3:
+; M3-NOT: smmla
+; M3: smull
+entry:
+  %tmp1 = mul nsw i32 %a, 3
+  %tmp2 = sdiv i32 %tmp1, 23
+  ret i32 %tmp2
+}