Properly pseudo-ize MOVCCr and MOVCCs.

[oota-llvm.git] / test / CodeGen / ARM / long_shift.ll

diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll
index 5e4f5730f8d21ae38b44db3bc1324cf0fd8df3f5..ab14de10ca252a770077fe09feb08df5368c99b7 100644 (file)
--- a/test/CodeGen/ARM/long_shift.ll
+++ b/test/CodeGen/ARM/long_shift.ll
@@ -26,7 +26,7 @@ define i32 @f2(i64 %x, i64 %y) {
 ; CHECK-NEXT: rsb     r3, r2, #32
 ; CHECK-NEXT: subs    r2, r2, #32
 ; CHECK-NEXT: orr     r0, r0, r1, lsl r3
-; CHECK-NEXT: movge   r0, r1, asr r2
+; CHECK-NEXT: asrge   r0, r1, r2
        %a = ashr i64 %x, %y
        %b = trunc i64 %a to i32
        ret i32 %b
@@ -38,7 +38,7 @@ define i32 @f3(i64 %x, i64 %y) {
 ; CHECK-NEXT: rsb     r3, r2, #32
 ; CHECK-NEXT: subs    r2, r2, #32
 ; CHECK-NEXT: orr     r0, r0, r1, lsl r3
-; CHECK-NEXT: movge   r0, r1, lsr r2
+; CHECK-NEXT: lsrge   r0, r1, r2
        %a = lshr i64 %x, %y
        %b = trunc i64 %a to i32
        ret i32 %b