ARM: prefer allocating VFP regs at stride 4 on Darwin.

[oota-llvm.git] / test / CodeGen / ARM / long.ll

diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll
index 772884c8cbece62b29c9862886e99ba353798b08..1807813d93052c700b93a753a617753cfe7ccc65 100644 (file)
--- a/test/CodeGen/ARM/long.ll
+++ b/test/CodeGen/ARM/long.ll
@@ -1,31 +1,90 @@
-; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm | grep "mov r1, #0" | wc -l | grep 4 &&
-; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #1" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep ".word.*2147483647" | wc -l | grep 2 &&
-; RUN: llvm-as < %s | llc -march=arm | grep "mov r0, #-2147483648" | wc -l | grep 1 &&
-; RUN: llvm-as < %s | llc -march=arm | grep ".word.*4294967295" | wc -l | grep 1
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 
-long %f1() {
+define i64 @f1() {
+; CHECK-LABEL: f1:
 entry:
-       ret long 0
+        ret i64 0
 }
 
-long %f2() {
+define i64 @f2() {
+; CHECK-LABEL: f2:
 entry:
-       ret long 1
+        ret i64 1
 }
 
-long %f3() {
+define i64 @f3() {
+; CHECK-LABEL: f3:
+; CHECK: mvn r0, #-2147483648
 entry:
-       ret long 2147483647
+        ret i64 2147483647
 }
 
-long %f4() {
+define i64 @f4() {
+; CHECK-LABEL: f4:
+; CHECK: mov r0, #-2147483648
 entry:
-       ret long 2147483648
+        ret i64 2147483648
 }
 
-long %f5() {
+define i64 @f5() {
+; CHECK-LABEL: f5:
+; CHECK: mvn r0, #0
+; CHECK: mvn r1, #-2147483648
 entry:
-       ret long 9223372036854775807
+        ret i64 9223372036854775807
+}
+
+define i64 @f6(i64 %x, i64 %y) {
+; CHECK-LABEL: f6:
+; CHECK: adds
+; CHECK: adc
+entry:
+        %tmp1 = add i64 %y, 1           ; <i64> [#uses=1]
+        ret i64 %tmp1
+}
+
+define void @f7() {
+; CHECK-LABEL: f7:
+entry:
+        %tmp = call i64 @f8( )          ; <i64> [#uses=0]
+        ret void
+}
+
+declare i64 @f8()
+
+define i64 @f9(i64 %a, i64 %b) {
+; CHECK-LABEL: f9:
+; CHECK: subs r
+; CHECK: sbc
+entry:
+        %tmp = sub i64 %a, %b           ; <i64> [#uses=1]
+        ret i64 %tmp
+}
+
+define i64 @f(i32 %a, i32 %b) {
+; CHECK-LABEL: f:
+; CHECK: smull
+entry:
+        %tmp = sext i32 %a to i64               ; <i64> [#uses=1]
+        %tmp1 = sext i32 %b to i64              ; <i64> [#uses=1]
+        %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
+        ret i64 %tmp2
+}
+
+define i64 @g(i32 %a, i32 %b) {
+; CHECK-LABEL: g:
+; CHECK: umull
+entry:
+        %tmp = zext i32 %a to i64               ; <i64> [#uses=1]
+        %tmp1 = zext i32 %b to i64              ; <i64> [#uses=1]
+        %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
+        ret i64 %tmp2
+}
+
+define i64 @f10() {
+; CHECK-LABEL: f10:
+entry:
+        %a = alloca i64, align 8                ; <i64*> [#uses=1]
+        %retval = load i64, i64* %a          ; <i64> [#uses=1]
+        ret i64 %retval
 }