ARM: Enable MachineScheduler and disable PostRAScheduler for swift.

[oota-llvm.git] / test / CodeGen / ARM / ldr_post.ll

diff --git a/test/CodeGen/ARM/ldr_post.ll b/test/CodeGen/ARM/ldr_post.ll
index 78b31352ba425de912209a66d11df74980deff25..139c6f45e52048e9775bfaa65b426e7f6ed2c676 100644 (file)
--- a/test/CodeGen/ARM/ldr_post.ll
+++ b/test/CodeGen/ARM/ldr_post.ll
@@ -1,11 +1,26 @@
-; RUN: llvm-upgrade < %s | llvm-as | llc -march=arm | \
-; RUN:   grep {ldr.*\\\[.*\],} | wc -l | grep 1
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s
 
-int %test(int %a, int %b, int %c) {
-       %tmp1 = mul int %a, %b
-       %tmp2 = cast int %tmp1 to int*
-       %tmp3 = load int* %tmp2
-        %tmp4 = sub int %tmp1, %c
-       %tmp5 = mul int %tmp4, %tmp3
-       ret int %tmp5
+; CHECK-LABEL: test1:
+; CHECK: ldr {{.*, \[.*]}}, -r2
+; CHECK-NOT: ldr
+define i32 @test1(i32 %a, i32 %b, i32 %c) {
+        %tmp1 = mul i32 %a, %b          ; <i32> [#uses=2]
+        %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
+        %tmp3 = load i32, i32* %tmp2         ; <i32> [#uses=1]
+        %tmp4 = sub i32 %tmp1, %c               ; <i32> [#uses=1]
+        %tmp5 = mul i32 %tmp4, %tmp3            ; <i32> [#uses=1]
+        ret i32 %tmp5
+}
+
+; CHECK-LABEL: test2:
+; CHECK: ldr {{.*, \[.*\]}}, #-16
+; CHECK-NOT: ldr
+define i32 @test2(i32 %a, i32 %b) {
+        %tmp1 = mul i32 %a, %b          ; <i32> [#uses=2]
+        %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
+        %tmp3 = load i32, i32* %tmp2         ; <i32> [#uses=1]
+        %tmp4 = sub i32 %tmp1, 16               ; <i32> [#uses=1]
+        %tmp5 = mul i32 %tmp4, %tmp3            ; <i32> [#uses=1]
+        ret i32 %tmp5
 }