[ARM][AArch64] Turn on by default interleaved access lowering

[oota-llvm.git] / test / CodeGen / ARM / iabs.ll

diff --git a/test/CodeGen/ARM/iabs.ll b/test/CodeGen/ARM/iabs.ll
index f10591f41f76526fda7747227413ed02eb6f7c3a..c52caf605dd1a615bae227989fa8414bd47e4b0e 100644 (file)
--- a/test/CodeGen/ARM/iabs.ll
+++ b/test/CodeGen/ARM/iabs.ll
@@ -1,16 +1,8 @@
-; RUN: llvm-as < %s | llc -march=arm -stats |& \
-; RUN:   grep {3 .*Number of machine instrs printed}
-; RUN: llvm-as < %s | llc -march=thumb -stats |& \
-; RUN:   grep {4 .*Number of machine instrs printed}
+; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s
 
 ;; Integer absolute value, should produce something as good as: ARM:
-;;   add r3, r0, r0, asr #31
-;;   eor r0, r3, r0, asr #31
-;;   bx lr
-;; Thumb:
-;;   asr r2, r0, #31
-;;   add r0, r0, r2
-;;   eor r0, r2
+;;   movs r0, r0
+;;   rsbmi r0, r0, #0
 ;;   bx lr
 
 define i32 @test(i32 %a) {
@@ -18,5 +10,25 @@ define i32 @test(i32 %a) {
         %b = icmp sgt i32 %a, -1
         %abs = select i1 %b, i32 %a, i32 %tmp1neg
         ret i32 %abs
+; CHECK:  cmp
+; CHECK:  rsbmi r0, r0, #0
+; CHECK:  bx lr
 }
 
+; rdar://11633193
+;; 3 instructions will be generated for abs(a-b):
+;;   subs
+;;   rsbmi
+;;   bx
+define i32 @test2(i32 %a, i32 %b) nounwind readnone ssp {
+entry:
+; CHECK: test2
+; CHECK: subs
+; CHECK-NEXT: rsbmi
+; CHECK-NEXT: bx
+  %sub = sub nsw i32 %a, %b
+  %cmp = icmp sgt i32 %sub, -1
+  %sub1 = sub nsw i32 0, %sub
+  %cond = select i1 %cmp, i32 %sub, i32 %sub1
+  ret i32 %cond
+}