[ARM][AArch64] Turn on by default interleaved access lowering

[oota-llvm.git] / test / CodeGen / ARM / global-merge-external.ll

diff --git a/test/CodeGen/ARM/global-merge-external.ll b/test/CodeGen/ARM/global-merge-external.ll
index 0dd3f477e9b39d0b3dba3f96043fbe7d051b9913..a9e0d199705a8b094b5bd39675c5c4ac6dbbe0be 100644 (file)
--- a/test/CodeGen/ARM/global-merge-external.ll
+++ b/test/CodeGen/ARM/global-merge-external.ll
@@ -11,7 +11,7 @@ define void @f1(i32 %a1, i32 %a2) {
 ;CHECK:          f1:
 ;CHECK:          ldr {{r[0-9]+}}, [[LABEL1:\.LCPI[0-9]+_[0-9]]]
 ;CHECK:          [[LABEL1]]:
-;CHECK-MERGE:    .long _MergedGlobals_x
+;CHECK-MERGE:    .long .L_MergedGlobals
 ;CHECK-NO-MERGE: .long {{_?x}}
   store i32 %a1, i32* @x, align 4
   store i32 %a2, i32* @y, align 4
@@ -22,24 +22,25 @@ define void @g1(i32 %a1, i32 %a2) {
 ;CHECK:          g1:
 ;CHECK:          ldr {{r[0-9]+}}, [[LABEL2:\.LCPI[0-9]+_[0-9]]]
 ;CHECK:          [[LABEL2]]:
-;CHECK-MERGE:    .long _MergedGlobals_x
+;CHECK-MERGE:    .long .L_MergedGlobals
 ;CHECK-NO-MERGE: .long {{_?y}}
   store i32 %a1, i32* @y, align 4
   store i32 %a2, i32* @z, align 4
   ret void
 }
 
-;CHECK-NO-MERGE-NOT: .globl _MergedGlobals_x
+;CHECK-NO-MERGE-NOT: .globl .L_MergedGlobals
 
-;CHECK-MERGE:  .type   _MergedGlobals_x,%object
-;CHECK-MERGE:  .globl  _MergedGlobals_x
-;CHECK-MERGE:  .align  2
-;CHECK-MERGE: _MergedGlobals_x:
-;CHECK-MERGE:  .size   _MergedGlobals_x, 12
+;CHECK-MERGE:  .type   .L_MergedGlobals,%object
+;CHECK-MERGE:  .local  .L_MergedGlobals
+;CHECK-MERGE:  .comm   .L_MergedGlobals,12,4
 
 ;CHECK-MERGE:  .globl  x
-;CHECK-MERGE: x = _MergedGlobals_x
+;CHECK-MERGE: x = .L_MergedGlobals
+;CHECK-MERGE: .size x, 4
 ;CHECK-MERGE:  .globl  y
-;CHECK-MERGE: y = _MergedGlobals_x+4
+;CHECK-MERGE: y = .L_MergedGlobals+4
+;CHECK-MERGE: .size y, 4
 ;CHECK-MERGE:  .globl  z
-;CHECK-MERGE: z = _MergedGlobals_x+8
+;CHECK-MERGE: z = .L_MergedGlobals+8
+;CHECK-MERGE: .size z, 4