[ARM][AArch64] Turn on by default interleaved access lowering

[oota-llvm.git] / test / CodeGen / ARM / fpconsts.ll

diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll
index 6a3a6d815d8d5a4c97b8b663a6b1705719a30318..5a45a9bd2ba5311291aceffac21a5cc3df42add7 100644 (file)
--- a/test/CodeGen/ARM/fpconsts.ll
+++ b/test/CodeGen/ARM/fpconsts.ll
@@ -1,33 +1,33 @@
-; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+vfp3 %s -o - | FileCheck %s
 
-define arm_apcscc float @t1(float %x) nounwind readnone optsize {
+define float @t1(float %x) nounwind readnone optsize {
 entry:
-; CHECK: t1:
-; CHECK: fconsts s1, 16
+; CHECK-LABEL: t1:
+; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
   %0 = fadd float %x, 4.000000e+00
   ret float %0
 }
 
-define arm_apcscc double @t2(double %x) nounwind readnone optsize {
+define double @t2(double %x) nounwind readnone optsize {
 entry:
-; CHECK: t2:
-; CHECK: fconstd d1, 8
+; CHECK-LABEL: t2:
+; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
   %0 = fadd double %x, 3.000000e+00
   ret double %0
 }
 
-define arm_apcscc double @t3(double %x) nounwind readnone optsize {
+define double @t3(double %x) nounwind readnone optsize {
 entry:
-; CHECK: t3:
-; CHECK: fconstd d1, 170
+; CHECK-LABEL: t3:
+; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
   %0 = fmul double %x, -1.300000e+01
   ret double %0
 }
 
-define arm_apcscc float @t4(float %x) nounwind readnone optsize {
+define float @t4(float %x) nounwind readnone optsize {
 entry:
-; CHECK: t4:
-; CHECK: fconsts s1, 184
+; CHECK-LABEL: t4:
+; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
   %0 = fmul float %x, -2.400000e+01
   ret float %0
 }