[ARM] When a bitcast is about to be turned into a VMOVDRR, try to combine it

[oota-llvm.git] / test / CodeGen / ARM / fast-isel-ldrh-strh-arm.ll

diff --git a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
index 572233ea6086b790bf45a314f2984d0c67439424..ca512970c9cf1786da333fe55547dad450eb7846 100644 (file)
--- a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
+++ b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
@@ -6,7 +6,7 @@ define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t1
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
-  %0 = load i16* %add.ptr, align 2
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #-16]
   ret i16 %0
 }
@@ -15,7 +15,7 @@ define zeroext i16 @t2(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t2
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 -16
-  %0 = load i16* %add.ptr, align 2
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #-32]
   ret i16 %0
 }
@@ -24,7 +24,7 @@ define zeroext i16 @t3(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t3
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 -127
-  %0 = load i16* %add.ptr, align 2
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #-254]
   ret i16 %0
 }
@@ -33,7 +33,7 @@ define zeroext i16 @t4(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t4
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
-  %0 = load i16* %add.ptr, align 2
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: mvn r{{[1-9]}}, #255
 ; ARM: add r0, r0, r{{[1-9]}}
 ; ARM: ldrh r0, [r0]
@@ -44,7 +44,7 @@ define zeroext i16 @t5(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t5
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 8
-  %0 = load i16* %add.ptr, align 2
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #16]
   ret i16 %0
 }
@@ -53,7 +53,7 @@ define zeroext i16 @t6(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t6
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 16
-  %0 = load i16* %add.ptr, align 2
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #32]
   ret i16 %0
 }
@@ -62,7 +62,7 @@ define zeroext i16 @t7(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t7
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 127
-  %0 = load i16* %add.ptr, align 2
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: ldrh r0, [r0, #254]
   ret i16 %0
 }
@@ -71,7 +71,7 @@ define zeroext i16 @t8(i16* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t8
   %add.ptr = getelementptr inbounds i16, i16* %a, i64 128
-  %0 = load i16* %add.ptr, align 2
+  %0 = load i16, i16* %add.ptr, align 2
 ; ARM: add r0, r0, #256
 ; ARM: ldrh r0, [r0]
   ret i16 %0
@@ -124,7 +124,7 @@ define signext i8 @t13(i8* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t13
   %add.ptr = getelementptr inbounds i8, i8* %a, i64 -8
-  %0 = load i8* %add.ptr, align 2
+  %0 = load i8, i8* %add.ptr, align 2
 ; ARM: ldrsb r0, [r0, #-8]
   ret i8 %0
 }
@@ -133,7 +133,7 @@ define signext i8 @t14(i8* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t14
   %add.ptr = getelementptr inbounds i8, i8* %a, i64 -255
-  %0 = load i8* %add.ptr, align 2
+  %0 = load i8, i8* %add.ptr, align 2
 ; ARM: ldrsb r0, [r0, #-255]
   ret i8 %0
 }
@@ -142,7 +142,7 @@ define signext i8 @t15(i8* nocapture %a) nounwind uwtable readonly ssp {
 entry:
 ; ARM: t15
   %add.ptr = getelementptr inbounds i8, i8* %a, i64 -256
-  %0 = load i8* %add.ptr, align 2
+  %0 = load i8, i8* %add.ptr, align 2
 ; ARM: mvn r{{[1-9]}}, #255
 ; ARM: add r0, r0, r{{[1-9]}}
 ; ARM: ldrsb r0, [r0]