ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2

[oota-llvm.git] / test / CodeGen / ARM / div.ll

diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll
index 1d7839439dcc2355b0d0ab9fc7c6f964f019a5a7..7b298fee42a52580a6a945ad7223b453c977ca65 100644 (file)
--- a/test/CodeGen/ARM/div.ll
+++ b/test/CodeGen/ARM/div.ll
@@ -1,29 +1,52 @@
-; RUN: llvm-as < %s | llc -march=arm &&
-; RUN: llvm-as < %s | llc -march=arm | grep __divsi3  &&
-; RUN: llvm-as < %s | llc -march=arm | grep __udivsi3 &&
-; RUN: llvm-as < %s | llc -march=arm | grep __modsi3  &&
-; RUN: llvm-as < %s | llc -march=arm | grep __umodsi3
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8    | FileCheck %s -check-prefix=CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift        | FileCheck %s -check-prefix=CHECK-HWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4    | FileCheck %s -check-prefix=CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f   | FileCheck %s -check-prefix=CHECK-SWDIV
+; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5    | FileCheck %s -check-prefix=CHECK-HWDIV
 
-int %f1(int %a, int %b) {
+define i32 @f1(i32 %a, i32 %b) {
 entry:
-       %tmp1 = div int %a, %b
-       ret int %tmp1
+; CHECK-SWDIV: f1
+; CHECK-SWDIV: __divsi3
+
+; CHECK-HWDIV: f1
+; CHECK-HWDIV: sdiv
+        %tmp1 = sdiv i32 %a, %b         ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-uint %f2(uint %a, uint %b) {
+define i32 @f2(i32 %a, i32 %b) {
 entry:
-       %tmp1 = div uint %a, %b
-       ret uint %tmp1
+; CHECK-SWDIV: f2
+; CHECK-SWDIV: __udivsi3
+
+; CHECK-HWDIV: f2
+; CHECK-HWDIV: udiv
+        %tmp1 = udiv i32 %a, %b         ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-int %f3(int %a, int %b) {
+define i32 @f3(i32 %a, i32 %b) {
 entry:
-       %tmp1 = rem int %a, %b
-       ret int %tmp1
+; CHECK-SWDIV: f3
+; CHECK-SWDIV: __modsi3
+
+; CHECK-HWDIV: f3
+; CHECK-HWDIV: sdiv
+; CHECK-HWDIV: mls
+        %tmp1 = srem i32 %a, %b         ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
 
-uint %f4(uint %a, uint %b) {
+define i32 @f4(i32 %a, i32 %b) {
 entry:
-       %tmp1 = rem uint %a, %b
-       ret uint %tmp1
+; CHECK-SWDIV: f4
+; CHECK-SWDIV: __umodsi3
+
+; CHECK-HWDIV: f4
+; CHECK-HWDIV: udiv
+; CHECK-HWDIV: mls
+        %tmp1 = urem i32 %a, %b         ; <i32> [#uses=1]
+        ret i32 %tmp1
 }
+