[X86][SSE] Added tests for i8/i16 vector shifts

[oota-llvm.git] / test / CodeGen / ARM / dagcombine-concatvector.ll

diff --git a/test/CodeGen/ARM/dagcombine-concatvector.ll b/test/CodeGen/ARM/dagcombine-concatvector.ll
index d8c6c6455801c867966bf88d6899d5ddb5515860..80ef2ab7b8bf3c0881e71c978df15e6a932de21b 100644 (file)
--- a/test/CodeGen/ARM/dagcombine-concatvector.ll
+++ b/test/CodeGen/ARM/dagcombine-concatvector.ll
@@ -1,11 +1,14 @@
-; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 -mcpu=generic | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
+; RUN: llc < %s -mtriple=thumbeb -target-abi apcs -mattr=v7,neon | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
 
 ; PR15525
 ; CHECK-LABEL: test1:
 ; CHECK: ldr.w [[REG:r[0-9]+]], [sp]
-; CHECK-NEXT: vmov     {{d[0-9]+}}, r1, r2
-; CHECK-NEXT: vmov     {{d[0-9]+}}, r3, [[REG]]
-; CHECK-NEXT: vst1.8   {{{d[0-9]+}}, {{d[0-9]+}}}, [r0]
+; CHECK-LE-NEXT: vmov  {{d[0-9]+}}, r1, r2
+; CHECK-LE-NEXT: vmov  {{d[0-9]+}}, r3, [[REG]]
+; CHECK-BE-NEXT: vmov  {{d[0-9]+}}, r2, r1
+; CHECK-BE: vmov       {{d[0-9]+}}, [[REG]], r3
+; CHECK: vst1.8        {{{d[0-9]+}}, {{d[0-9]+}}}, [r0]
 ; CHECK-NEXT: bx       lr
 define void @test1(i8* %arg, [4 x i64] %vec.coerce) {
 bb: