define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
%0 = icmp eq %struct.list_head* %list, null
br i1 %0, label %bb2, label %bb
bb:
-; CHECK: LBB0_2:
-; CHECK: bne LBB0_2
-; CHECK-NOT: b LBB0_2
+; CHECK: LBB0_1:
+; CHECK: bne LBB0_1
+; CHECK-NOT: b LBB0_1
; CHECK: bx lr
%list_addr.05 = phi %struct.list_head* [ %2, %bb ], [ %list, %entry ]
%next.04 = phi %struct.list_head* [ %list_addr.05, %bb ], [ null, %entry ]
- %1 = getelementptr inbounds %struct.list_head* %list_addr.05, i32 0, i32 0
- %2 = load %struct.list_head** %1, align 4
+ %1 = getelementptr inbounds %struct.list_head, %struct.list_head* %list_addr.05, i32 0, i32 0
+ %2 = load %struct.list_head*, %struct.list_head** %1, align 4
store %struct.list_head* %next.04, %struct.list_head** %1, align 4
%3 = icmp eq %struct.list_head* %2, null
br i1 %3, label %bb2, label %bb
; rdar://8117827
define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: beq LBB1_[[RET:.]]
%0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1]
br i1 %0, label %bb5, label %bb.nph15
%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2]
%sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1]
%tmp17 = sub i32 %i.07, %indvar ; <i32> [#uses=1]
- %scevgep = getelementptr i32* %src, i32 %tmp17 ; <i32*> [#uses=1]
- %1 = load i32* %scevgep, align 4 ; <i32> [#uses=1]
+ %scevgep = getelementptr i32, i32* %src, i32 %tmp17 ; <i32*> [#uses=1]
+ %1 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1]
%2 = add nsw i32 %1, %sum.08 ; <i32> [#uses=2]
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
%exitcond = icmp eq i32 %indvar.next, %size ; <i1> [#uses=1]