%struct.Foo = type { i8* }
-; ARM: foo
-; THUMB: foo
-; T2: foo
+; ARM-LABEL: foo:
+; THUMB-LABEL: foo:
+; T2-LABEL: foo:
define %struct.Foo* @foo(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 {
entry:
%scevgep = getelementptr %struct.Foo, %struct.Foo* %this, i32 1
%acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ]
%lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8**
%scevgep5 = getelementptr i8*, i8** %lsr.iv24, i32 -1
- %tmp2 = load i8** %scevgep5
+ %tmp2 = load i8*, i8** %scevgep5
%0 = ptrtoint i8* %tmp2 to i32
; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3
; V8-NEXT: beq
; V8-NEXT: %tailrecurse.switch
; V8: cmp
-; V8-NEXT: beq
+; V8-NEXT: bne
; V8-NEXT: b
; The trailing space in the last line checks that the branch is unconditional
switch i32 %and, label %sw.epilog [
i32 1, label %sw.bb
i32 3, label %sw.bb6
i32 2, label %sw.bb8
- ]
+ ], !prof !1
sw.bb: ; preds = %tailrecurse.switch, %tailrecurse
%shl = shl i32 %acc.tr, 1
%struct.S = type { i8* (i8*)*, [1 x i8] }
-; ARM: bar
-; THUMB: bar
-; T2: bar
+; ARM-LABEL: bar:
+; THUMB-LABEL: bar:
+; T2-LABEL: bar:
; V8-LABEL: bar:
define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly {
entry:
%0 = getelementptr inbounds %struct.S, %struct.S* %x, i32 0, i32 1, i32 0
- %1 = load i8* %0, align 1
+ %1 = load i8, i8* %0, align 1
%2 = zext i8 %1 to i32
; ARM: ands
; THUMB: ands
bb: ; preds = %entry
; V8-NEXT: %bb
%5 = getelementptr inbounds %struct.S, %struct.S* %y, i32 0, i32 1, i32 0
- %6 = load i8* %5, align 1
+ %6 = load i8, i8* %5, align 1
%7 = zext i8 %6 to i32
; ARM: andsne
; THUMB: ands
return: ; preds = %bb2, %bb, %entry
ret i8 1
}
+
+
+; We were looking through multiple COPY instructions to find an AND we might
+; fold into a TST, but in doing so we changed the register being tested allowing
+; folding of unrelated tests (in this case, a TST against r1 was eliminated in
+; favour of an AND of r0).
+
+; ARM-LABEL: test_tst_assessment:
+; THUMB-LABEL: test_tst_assessment:
+; T2-LABEL: test_tst_assessment:
+; V8-LABEL: test_tst_assessment:
+define i32 @test_tst_assessment(i1 %lhs, i1 %rhs) {
+ %lhs32 = zext i1 %lhs to i32
+ %rhs32 = zext i1 %rhs to i32
+ %diff = sub nsw i32 %lhs32, %rhs32
+; ARM: tst r1, #1
+; THUMB: movs [[RTMP:r[0-9]+]], #1
+; THUMB: tst r1, [[RTMP]]
+; T2: tst.w r1, #1
+; V8: tst.w r1, #1
+ ret i32 %diff
+}
+
+!1 = !{!"branch_weights", i32 1, i32 1, i32 3, i32 2 }