ARM: Enable MachineScheduler and disable PostRAScheduler for swift.

[oota-llvm.git] / test / CodeGen / ARM / adv-copy-opt.ll

diff --git a/test/CodeGen/ARM/adv-copy-opt.ll b/test/CodeGen/ARM/adv-copy-opt.ll
index f71bf78b62c4b0f69f09b29b9a61b80b0d192a1d..395be3457203bba3a018fa8107800a9202adc411 100644 (file)
--- a/test/CodeGen/ARM/adv-copy-opt.ll
+++ b/test/CodeGen/ARM/adv-copy-opt.ll
@@ -11,25 +11,25 @@
 ; r0 = r0 / r2
 ; r1 = r1 / r3
 ;
-; NOOPT: vmov  [[B:d[0-9]+]], r2, r3
-; NOOPT-NEXT: vmov     [[A:d[0-9]+]], r0, r1
+; NOOPT: vmov  [[A:d[0-9]+]], r0, r1
+; NOOPT-NEXT: vmov     [[B:d[0-9]+]], r2, r3
 ; Move the low part of B into a register.
 ; Unfortunately, we cannot express that the 's' register is the low
 ; part of B, i.e., sIdx == BIdx x 2. E.g., B = d1, B_low = s2.
 ; NOOPT-NEXT: vmov     [[B_LOW:r[0-9]+]], s{{[0-9]+}}
-; NOOPT-NEXT: vmov     [[A_LOW:r[0-9]+]], s{{[0-9]+}}
-; NOOPT-NEXT: udiv     [[RES_LOW:r[0-9]+]], [[A_LOW]], [[B_LOW]]
 ; NOOPT-NEXT: vmov     [[B_HIGH:r[0-9]+]], s{{[0-9]+}}
+; NOOPT-NEXT: vmov     [[A_LOW:r[0-9]+]], s{{[0-9]+}}
 ; NOOPT-NEXT: vmov     [[A_HIGH:r[0-9]+]], s{{[0-9]+}}
-; NOOPT-NEXT: udiv     [[RES_HIGH:r[0-9]+]], [[A_HIGH]], [[B_HIGH]]
+; NOOPT-NEXT: udiv     [[RES_LOW:r[0-9]+]], [[A_LOW]], [[B_LOW]]
 ; NOOPT-NEXT: vmov.32  [[RES:d[0-9]+]][0], [[RES_LOW]]
+; NOOPT-NEXT: udiv     [[RES_HIGH:r[0-9]+]], [[A_HIGH]], [[B_HIGH]]
 ; NOOPT-NEXT: vmov.32  [[RES]][1], [[RES_HIGH]]
 ; NOOPT-NEXT: vmov     r0, r1, [[RES]]
 ; NOOPT-NEXT: bx       lr
 ;
 ; OPT-NOT: vmov
-; OPT:         udiv    r0, r0, r2
-; OPT-NEXT: udiv       r1, r1, r3
+; OPT: udiv    r1, r1, r3
+; OPT-NEXT:    udiv    r0, r0, r2
 ; OPT-NEXT: bx lr
 define <2 x i32> @simpleVectorDiv(<2 x i32> %A, <2 x i32> %B) nounwind {
 entry: