[ARM] Define subtarget feature "reserve-r9", which is used to decide

[oota-llvm.git] / test / CodeGen / ARM / 2011-04-07-schediv.ll

diff --git a/test/CodeGen/ARM/2011-04-07-schediv.ll b/test/CodeGen/ARM/2011-04-07-schediv.ll
index 19f756f513647ba270c51d24b20ab84000ccea3f..7f603157c5d3f62117602bd793de0351cf8699f6 100644 (file)
--- a/test/CodeGen/ARM/2011-04-07-schediv.ll
+++ b/test/CodeGen/ARM/2011-04-07-schediv.ll
@@ -12,16 +12,16 @@ entry:
 
 ; Make sure the scheduler schedules all uses of the preincrement
 ; induction variable before defining the postincrement value.
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: %bb
 ; CHECK-NOT: mov
 bb:                                               ; preds = %entry, %bb
   %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]
   %tmp = mul i32 %j.05, %src_copy_start_index
-  %uglygep = getelementptr i8* %src_copy_start6, i32 %tmp
+  %uglygep = getelementptr i8, i8* %src_copy_start6, i32 %tmp
   %src_copy_start_addr.04 = bitcast i8* %uglygep to float*
-  %dst_copy_start_addr.03 = getelementptr float* %dst_copy_start, i32 %j.05
-  %1 = load float* %src_copy_start_addr.04, align 4
+  %dst_copy_start_addr.03 = getelementptr float, float* %dst_copy_start, i32 %j.05
+  %1 = load float, float* %src_copy_start_addr.04, align 4
   store float %1, float* %dst_copy_start_addr.03, align 4
   %2 = add i32 %j.05, 1
   %exitcond = icmp eq i32 %2, %src_width