Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate

[oota-llvm.git] / test / CodeGen / ARM / 2009-08-21-PostRAKill.ll

diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
index 17cbba2800b09ecb6f53aa6375160b2aa336389f..c598fe6e2e1a91ea7c3f6c5f456feddcf66afec0 100644 (file)
--- a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
+++ b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2 -mcpu=cortex-a8 -disable-post-RA-scheduler=0 -avoid-hazards
+; RUN: llc < %s -march=arm -mattr=+vfp2 -post-RA-scheduler -mcpu=cortex-a8
 
 ; ModuleID = '<stdin>'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
@@ -7,7 +7,7 @@ target triple = "armv7-apple-darwin9"
 %struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* }
 @g = common global %struct.tree* null
 
-define arm_apcscc %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind {
+define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind {
 entry:
   %t.idx51.val.i = load double* null              ; <double> [#uses=1]
   br i1 undef, label %bb4.i, label %bb.i