[X86][SSE] Added tests for i8/i16 vector shifts

[oota-llvm.git] / test / CodeGen / ARM / 2009-06-30-RegScavengerAssert5.ll

diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
index 277283dc0889064026dfe29e5c9d0061b5596a93..b3c91ed3fb0db9ec96141761e1c8fd054645bfdf 100644 (file)
--- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
+++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll
@@ -2,7 +2,7 @@
 
 @XX = external global i32*             ; <i32**> [#uses=1]
 
-define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
+define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind {
 entry:
        br i1 undef, label %bb5, label %bb
 
@@ -28,7 +28,7 @@ bb11:         ; preds = %bb9
        br i1 undef, label %bb15, label %bb12
 
 bb12:          ; preds = %bb11
-       %0 = load i32** @XX, align 4            ; <i32*> [#uses=0]
+       %0 = load i32*, i32** @XX, align 4              ; <i32*> [#uses=0]
        br label %bb228.i
 
 bb74.i:                ; preds = %bb228.i