[ARM] Enable shrink-wrapping by default.

[oota-llvm.git] / test / CodeGen / ARM / 2007-01-19-InfiniteLoop.ll

diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
index ee63656b26d398f9f75e283bf9f397fd2f72a8ce..4ba81e01ad318bb865d72c5e1a0aee76455c81ba 100644 (file)
--- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
+++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -1,28 +1,33 @@
-; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck --check-prefix=DOMAIN %s
 
+; The execution domain checking code would translate vmovs to vorr whether or not
+; we had NEON instructions. Verify we don't if we're not compiled with NEON.
+; DOMAIN-NOT: vorr
 @quant_coef = external global [6 x [4 x [4 x i32]]]            ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
 @dequant_coef = external global [6 x [4 x [4 x i32]]]          ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
 @A = external global [4 x [4 x i32]]           ; <[4 x [4 x i32]]*> [#uses=1]
 
-; CHECK: dct_luma_sp:
+; CHECK-LABEL: dct_luma_sp:
 define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
 entry:
 ; Make sure to use base-updating stores for saving callee-saved registers.
+; CHECK: push
 ; CHECK-NOT: sub sp
-; CHECK: vstmdb sp!
+; CHECK: push 
        %predicted_block = alloca [4 x [4 x i32]], align 4              ; <[4 x [4 x i32]]*> [#uses=1]
        br label %cond_next489
 
 cond_next489:          ; preds = %cond_false, %bb471
-       %j.7.in = load i8* null         ; <i8> [#uses=1]
-       %i.8.in = load i8* null         ; <i8> [#uses=1]
+       %j.7.in = load i8, i8* null             ; <i8> [#uses=1]
+       %i.8.in = load i8, i8* null             ; <i8> [#uses=1]
        %i.8 = zext i8 %i.8.in to i32           ; <i32> [#uses=4]
        %j.7 = zext i8 %j.7.in to i32           ; <i32> [#uses=4]
-       %tmp495 = getelementptr [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7            ; <i32*> [#uses=2]
-       %tmp496 = load i32* %tmp495             ; <i32> [#uses=2]
-       %tmp502 = load i32* null                ; <i32> [#uses=1]
-       %tmp542 = getelementptr [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7            ; <i32*> [#uses=1]
-       %tmp543 = load i32* %tmp542             ; <i32> [#uses=1]
+       %tmp495 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7           ; <i32*> [#uses=2]
+       %tmp496 = load i32, i32* %tmp495                ; <i32> [#uses=2]
+       %tmp502 = load i32, i32* null           ; <i32> [#uses=1]
+       %tmp542 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7             ; <i32*> [#uses=1]
+       %tmp543 = load i32, i32* %tmp542                ; <i32> [#uses=1]
        %tmp548 = ashr i32 0, 0         ; <i32> [#uses=3]
        %tmp561 = sub i32 0, %tmp496            ; <i32> [#uses=3]
        %abscond563 = icmp sgt i32 %tmp561, -1          ; <i1> [#uses=1]
@@ -34,10 +39,10 @@ cond_next489:               ; preds = %cond_false, %bb471
        br i1 %tmp579, label %bb712, label %cond_next589
 
 cond_next589:          ; preds = %cond_next489
-       %tmp605 = getelementptr [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7          ; <i32*> [#uses=1]
-       %tmp606 = load i32* %tmp605             ; <i32> [#uses=1]
-       %tmp612 = load i32* null                ; <i32> [#uses=1]
-       %tmp629 = load i32* null                ; <i32> [#uses=1]
+       %tmp605 = getelementptr [6 x [4 x [4 x i32]]], [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7           ; <i32*> [#uses=1]
+       %tmp606 = load i32, i32* %tmp605                ; <i32> [#uses=1]
+       %tmp612 = load i32, i32* null           ; <i32> [#uses=1]
+       %tmp629 = load i32, i32* null           ; <i32> [#uses=1]
        %tmp629a = sitofp i32 %tmp629 to double         ; <double> [#uses=1]
        %tmp631 = fmul double %tmp629a, 0.000000e+00            ; <double> [#uses=1]
        %tmp632 = fadd double 0.000000e+00, %tmp631             ; <double> [#uses=1]
@@ -84,9 +89,9 @@ bb737:                ; preds = %cond_false689
 
 cond_true740:          ; preds = %bb737
        %tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 )           ; <i32> [#uses=1]
-       %tmp780 = load i32* null                ; <i32> [#uses=1]
-       %tmp785 = getelementptr [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7          ; <i32*> [#uses=1]
-       %tmp786 = load i32* %tmp785             ; <i32> [#uses=1]
+       %tmp780 = load i32, i32* null           ; <i32> [#uses=1]
+       %tmp785 = getelementptr [4 x [4 x i32]], [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7         ; <i32*> [#uses=1]
+       %tmp786 = load i32, i32* %tmp785                ; <i32> [#uses=1]
        %tmp781 = mul i32 %tmp780, %tmp761              ; <i32> [#uses=1]
        %tmp787 = mul i32 %tmp781, %tmp786              ; <i32> [#uses=1]
        %tmp789 = shl i32 %tmp787, 0            ; <i32> [#uses=1]
@@ -95,7 +100,7 @@ cond_true740:                ; preds = %bb737
 
 cond_next791:          ; preds = %cond_true740, %bb737
        %ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ]             ; <i32> [#uses=1]
-       %tmp796 = load i32* %tmp495             ; <i32> [#uses=1]
+       %tmp796 = load i32, i32* %tmp495                ; <i32> [#uses=1]
        %tmp798 = add i32 %tmp796, %ilev.1              ; <i32> [#uses=1]
        %tmp812 = mul i32 0, %tmp502            ; <i32> [#uses=0]
        %tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 )           ; <i32> [#uses=0]