AArch64/ARM64: enable more AArch64 tests on ARM64.

[oota-llvm.git] / test / CodeGen / AArch64 / fcvt-fixed.ll

diff --git a/test/CodeGen/AArch64/fcvt-fixed.ll b/test/CodeGen/AArch64/fcvt-fixed.ll
index 0f7b95b2a48f8b747848be7f0816ed6d18f39874..5d7c83ebfb3669f3bc8bb46c819c644ff8c123b3 100644 (file)
--- a/test/CodeGen/AArch64/fcvt-fixed.ll
+++ b/test/CodeGen/AArch64/fcvt-fixed.ll
@@ -1,10 +1,15 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -O0 | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-none-linux-gnu | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 -O0
+
+; (The O0 test is to make sure FastISel still constrains its operands properly
+; and the verifier doesn't trigger).
 
 @var32 = global i32 0
 @var64 = global i64 0
 
 define void @test_fcvtzs(float %flt, double %dbl) {
-; CHECK: test_fcvtzs:
+; CHECK-LABEL: test_fcvtzs:
 
   %fix1 = fmul float %flt, 128.0
   %cvt1 = fptosi float %fix1 to i32
@@ -50,7 +55,7 @@ define void @test_fcvtzs(float %flt, double %dbl) {
 }
 
 define void @test_fcvtzu(float %flt, double %dbl) {
-; CHECK: test_fcvtzu:
+; CHECK-LABEL: test_fcvtzu:
 
   %fix1 = fmul float %flt, 128.0
   %cvt1 = fptoui float %fix1 to i32
@@ -99,7 +104,7 @@ define void @test_fcvtzu(float %flt, double %dbl) {
 @vardouble = global double 0.0
 
 define void @test_scvtf(i32 %int, i64 %long) {
-; CHECK: test_scvtf:
+; CHECK-LABEL: test_scvtf:
 
   %cvt1 = sitofp i32 %int to float
   %fix1 = fdiv float %cvt1, 128.0
@@ -145,7 +150,7 @@ define void @test_scvtf(i32 %int, i64 %long) {
 }
 
 define void @test_ucvtf(i32 %int, i64 %long) {
-; CHECK: test_ucvtf:
+; CHECK-LABEL: test_ucvtf:
 
   %cvt1 = uitofp i32 %int to float
   %fix1 = fdiv float %cvt1, 128.0