[DAGCombiner] Attempt to mask vectors before zero extension instead of after.

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-vector-ext.ll

diff --git a/test/CodeGen/AArch64/arm64-vector-ext.ll b/test/CodeGen/AArch64/arm64-vector-ext.ll
index 5bee1611e6c64d1cb8f9f9cf2d7e38756a28a15b..994a9956cf7f88ed27cc4538d970f67104726f50 100644 (file)
--- a/test/CodeGen/AArch64/arm64-vector-ext.ll
+++ b/test/CodeGen/AArch64/arm64-vector-ext.ll
@@ -1,27 +1,27 @@
-; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
-
-;CHECK: @func30
-;CHECK: ushll.4s  v0, v0, #0
-;CHECK: movi.4s v1, #0x1
-;CHECK: and.16b v0, v0, v1
-;CHECK: str  q0, [x0]
-;CHECK: ret
-
-%T0_30 = type <4 x i1>
-%T1_30 = type <4 x i32>
-define void @func30(%T0_30 %v0, %T1_30* %p1) {
-  %r = zext %T0_30 %v0 to %T1_30
-  store %T1_30 %r, %T1_30* %p1
-  ret void
-}
-
-; Extend from v1i1 was crashing things (PR20791). Make sure we do something
-; sensible instead.
-define <1 x i32> @autogen_SD7918() {
-; CHECK-LABEL: autogen_SD7918
-; CHECK: movi d0, #0000000000000000
-; CHECK-NEXT: ret
-  %I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0
-  %ZE = zext <1 x i1> %I29 to <1 x i32>
-  ret <1 x i32> %ZE
-}
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s\r
+\r
+;CHECK: @func30\r
+;CHECK: movi.4h v1, #0x1\r
+;CHECK: and.8b v0, v0, v1\r
+;CHECK: ushll.4s  v0, v0, #0\r
+;CHECK: str  q0, [x0]\r
+;CHECK: ret\r
+\r
+%T0_30 = type <4 x i1>\r
+%T1_30 = type <4 x i32>\r
+define void @func30(%T0_30 %v0, %T1_30* %p1) {\r
+  %r = zext %T0_30 %v0 to %T1_30\r
+  store %T1_30 %r, %T1_30* %p1\r
+  ret void\r
+}\r
+\r
+; Extend from v1i1 was crashing things (PR20791). Make sure we do something\r
+; sensible instead.\r
+define <1 x i32> @autogen_SD7918() {\r
+; CHECK-LABEL: autogen_SD7918\r
+; CHECK: movi d0, #0000000000000000\r
+; CHECK-NEXT: ret\r
+  %I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0\r
+  %ZE = zext <1 x i1> %I29 to <1 x i32>\r
+  ret <1 x i32> %ZE\r
+}\r