AArch64/ARM64: enable more AArch64 tests on ARM64.

[oota-llvm.git] / test / CodeGen / AArch64 / 128bit_load_store.ll

diff --git a/test/CodeGen/AArch64/128bit_load_store.ll b/test/CodeGen/AArch64/128bit_load_store.ll
index 502fd70791b2601eb7f6f2334883bbe25d7938af..2360e858b574c8a9adbff15f91e067e621b4e5e1 100644 (file)
--- a/test/CodeGen/AArch64/128bit_load_store.ll
+++ b/test/CodeGen/AArch64/128bit_load_store.ll
@@ -1,7 +1,8 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon| FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
 
 define void @test_store_f128(fp128* %ptr, fp128 %val) #0 {
-; CHECK: test_store_f128
+; CHECK-LABEL: test_store_f128
 ; CHECK: str    {{q[0-9]+}}, [{{x[0-9]+}}]
 entry:
   store fp128 %val, fp128* %ptr, align 16
@@ -9,7 +10,7 @@ entry:
 }
 
 define fp128 @test_load_f128(fp128* readonly %ptr) #2 {
-; CHECK: test_load_f128
+; CHECK-LABEL: test_load_f128
 ; CHECK: ldr    {{q[0-9]+}}, [{{x[0-9]+}}]
 entry:
   %0 = load fp128* %ptr, align 16
@@ -17,9 +18,12 @@ entry:
 }
 
 define void @test_vstrq_p128(i128* %ptr, i128 %val) #0 {
-; CHECK: test_vstrq_p128
-; CHECK: str   {{x[0-9]+}}, [{{x[0-9]+}}, #8]
-; CHECK-NEXT: str       {{x[0-9]+}}, [{{x[0-9]+}}]
+; CHECK-ARM64-LABEL: test_vstrq_p128
+; CHECK-ARM64: stp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
+
+; CHECK-AARCH64-LABEL: test_vstrq_p128
+; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}, #8]
+; CHECK-AARCH64: str {{x[0-9]+}}, [{{x[0-9]+}}]
 entry:
   %0 = bitcast i128* %ptr to fp128*
   %1 = bitcast i128 %val to fp128
@@ -28,9 +32,12 @@ entry:
 }
 
 define i128 @test_vldrq_p128(i128* readonly %ptr) #2 {
-; CHECK: test_vldrq_p128
-; CHECK: ldr   {{x[0-9]+}}, [{{x[0-9]+}}]
-; CHECK-NEXT: ldr      {{x[0-9]+}}, [{{x[0-9]+}}, #8]
+; CHECK-ARM64-LABEL: test_vldrq_p128
+; CHECK-ARM64: ldp {{x[0-9]+}}, {{x[0-9]+}}, [{{x[0-9]+}}]
+
+; CHECK-AARCH64-LABEL: test_vldrq_p128
+; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}]
+; CHECK-AARCH64: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8]
 entry:
   %0 = bitcast i128* %ptr to fp128*
   %1 = load fp128* %0, align 16
@@ -39,7 +46,7 @@ entry:
 }
 
 define void @test_ld_st_p128(i128* nocapture %ptr) #0 {
-; CHECK: test_ld_st_p128
+; CHECK-LABEL: test_ld_st_p128
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}]
 ; CHECK-NEXT: str      {{q[0-9]+}}, [{{x[0-9]+}}, #16]
 entry: