Ensure bitcode encoding of instructions and their operands stays stable.

[oota-llvm.git] / test / Bitcode / vectorInstructions.3.2.ll

diff --git a/test/Bitcode/vectorInstructions.3.2.ll b/test/Bitcode/vectorInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..b24ef75
--- /dev/null
+++ b/test/Bitcode/vectorInstructions.3.2.ll
@@ -0,0 +1,34 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread vector operations of\r
+; older bitcode files.\r
+\r
+define void @extractelement(<2 x i8> %x1){\r
+entry:\r
+; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0\r
+  %res1 = extractelement <2 x i8> %x1, i32 0\r
+  \r
+  ret void\r
+}\r
+\r
+define void @insertelement(<2 x i8> %x1){\r
+entry:\r
+; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0\r
+  %res1 = insertelement <2 x i8> %x1, i8 0, i32 0\r
+  \r
+  ret void\r
+}\r
+\r
+define void @shufflevector(<2 x i8> %x1){\r
+entry:\r
+; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>\r
+  %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>\r
+\r
+; CHECK-NEXT: %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>\r
+  %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>\r
+  \r
+  ret void\r
+}\r
+\r
+\r