Ensure bitcode encoding of instructions and their operands stays stable.

[oota-llvm.git] / test / Bitcode / binaryFloatInstructions.3.2.ll

diff --git a/test/Bitcode/binaryFloatInstructions.3.2.ll b/test/Bitcode/binaryFloatInstructions.3.2.ll
new file mode 100644 (file)
index 0000000..f94d82d
--- /dev/null
+++ b/test/Bitcode/binaryFloatInstructions.3.2.ll
@@ -0,0 +1,120 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s\r
+\r
+; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.\r
+; The test checks that LLVM does not misread binary float instructions from\r
+; older bitcode files.\r
+\r
+define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){\r
+entry:\r
+; CHECK: %res1 = fadd float %x1, %x1\r
+  %res1 = fadd float %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = fadd double %x2, %x2\r
+  %res2 = fadd double %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = fadd half %x3, %x3\r
+  %res3 = fadd half %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4\r
+  %res4 = fadd fp128 %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5\r
+  %res5 = fadd x86_fp80 %x5, %x5\r
+  \r
+; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6\r
+  %res6 = fadd ppc_fp128 %x6, %x6\r
+  \r
+  ret void\r
+}\r
+\r
+define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){\r
+entry:\r
+; CHECK: %res1 = fadd <2 x float> %x1, %x1\r
+  %res1 = fadd <2 x float> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2\r
+  %res2 = fadd <3 x float> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3\r
+  %res3 = fadd <4 x float> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4\r
+  %res4 = fadd <8 x float> %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5\r
+  %res5 = fadd <16 x float> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){\r
+entry:\r
+; CHECK: %res1 = fadd <2 x double> %x1, %x1\r
+  %res1 = fadd <2 x double> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2\r
+  %res2 = fadd <3 x double> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3\r
+  %res3 = fadd <4 x double> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4\r
+  %res4 = fadd <8 x double> %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5\r
+  %res5 = fadd <16 x double> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){\r
+entry:\r
+; CHECK: %res1 = fadd <2 x half> %x1, %x1\r
+  %res1 = fadd <2 x half> %x1, %x1\r
+\r
+; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2\r
+  %res2 = fadd <3 x half> %x2, %x2\r
+\r
+; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3\r
+  %res3 = fadd <4 x half> %x3, %x3\r
+\r
+; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4\r
+  %res4 = fadd <8 x half> %x4, %x4\r
+\r
+; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5\r
+  %res5 = fadd <16 x half> %x5, %x5\r
+  \r
+  ret void\r
+}\r
+\r
+define void @fsub(float %x1){\r
+entry:\r
+; CHECK: %res1 = fsub float %x1, %x1\r
+  %res1 = fsub float %x1, %x1\r
+\r
+  ret void\r
+}\r
+\r
+define void @fmul(float %x1){\r
+entry:\r
+; CHECK: %res1 = fmul float %x1, %x1\r
+  %res1 = fmul float %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @fdiv(float %x1){\r
+entry:\r
+; CHECK: %res1 = fdiv float %x1, %x1\r
+  %res1 = fdiv float %x1, %x1\r
+  \r
+  ret void\r
+}\r
+\r
+define void @frem(float %x1){\r
+entry:\r
+; CHECK: %res1 = frem float %x1, %x1\r
+  %res1 = frem float %x1, %x1\r
+\r
+  ret void\r
+}\r