Have more strict type checks when creating BinOp nodes in BitcodeReader

[oota-llvm.git] / test / Bitcode / arm32_neon_vcnt_upgrade.ll

diff --git a/test/Bitcode/arm32_neon_vcnt_upgrade.ll b/test/Bitcode/arm32_neon_vcnt_upgrade.ll
index b3f2f03d1086f1bd6e2f58a581a23b0b06012b9e..0032c4a9b7a3cacc60845a6f12130d2e2a36c0ca 100644 (file)
--- a/test/Bitcode/arm32_neon_vcnt_upgrade.ll
+++ b/test/Bitcode/arm32_neon_vcnt_upgrade.ll
@@ -1,12 +1,22 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
-; NB: currently tests only vclz, should also test vcnt and vcls
+; RUN: verify-uselistorder < %s
+; Tests vclz and vcnt
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 ;CHECK: @vclz16
-        %tmp1 = load <4 x i16>* %A
+        %tmp1 = load <4 x i16>, <4 x i16>* %A
         %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
 ;CHECK: {{call.*@llvm.ctlz.v4i16\(<4 x i16>.*, i1 false}}
         ret <4 x i16> %tmp2
 }
 
+define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
+;CHECK: @vcnt8
+        %tmp1 = load <8 x i8>, <8 x i8>* %A
+        %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1)
+;CHECK: call <8 x i8> @llvm.ctpop.v8i8(<8 x i8>
+        ret <8 x i8> %tmp2
+}
+
 declare <4 x i16>  @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
+declare <8 x i8>  @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone