llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.

[oota-llvm.git] / lib / Target / XCore / XCoreInstrInfo.td

diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index 15e51f51b119fbde7ce4d42e8a5aa18397b79bcd..65cd4fe955591207df995af24ab96e119aa66206 100644 (file)
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -50,17 +50,17 @@ def SDT_XCoreAddress    : SDTypeProfile<1, 1,
                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
 
 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
-                          []>;
+                           []>;
 
 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
-                          []>;
+                           []>;
 
 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
-                          []>;
+                           []>;
 
 def SDT_XCoreStwsp    : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
-def XCoreStwsp         : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
-                          [SDNPHasChain]>;
+def XCoreStwsp        : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
+                               [SDNPHasChain]>;
 
 // These are target-independent nodes, but have target-specific formats.
 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
@@ -349,6 +349,18 @@ def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                             [(callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
+def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
+                             "${:comment} LDWFI $dst, $addr",
+                             [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
+
+def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
+                             "${:comment} LDAWFI $dst, $addr",
+                             [(set GRRegs:$dst, ADDRspii:$addr)]>;
+
+def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
+                            "${:comment} STWFI $src, $addr",
+                            [(store GRRegs:$src, ADDRspii:$addr)]>;
+
 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded by the
 // scheduler into a branch sequence.
 let usesCustomDAGSchedInserter = 1 in {
@@ -543,51 +555,41 @@ let mayLoad = 1, isReMaterializable = 1 in
 defm LDWCP : FRU6_LRU6_cp<"ldw">;
 
 let Uses = [SP] in {
-let mayStore=1 in
+let mayStore=1 in {
 def STWSP_ru6 : _FRU6<
-                 (outs), (ins GRRegs:$dst, MEMii:$b),
-                 "stw $dst, sp[$b]",
-                 []>;
+                 (outs), (ins GRRegs:$val, i32imm:$index),
+                 "stw $val, sp[$index]",
+                 [(XCoreStwsp GRRegs:$val, immU6:$index)]>;
 
 def STWSP_lru6 : _FLRU6<
-                 (outs), (ins GRRegs:$dst, MEMii:$b),
-                 "stw $dst, sp[$b]",
-                 [(store GRRegs:$dst, ADDRspii:$b)]>;
-
-let mayStore=1 in
-def STWSP_ru6_2 : _FRU6<
-                 (outs), (ins GRRegs:$dst, i32imm:$b),
-                 "stw $dst, sp[$b]",
-                 []>;
-
-def STWSP_lru6_2 : _FLRU6<
-                 (outs), (ins GRRegs:$dst, i32imm:$b),
-                 "stw $dst, sp[$b]",
-                 [(store GRRegs:$dst, ADDRspii:$b)]>;
+                 (outs), (ins GRRegs:$val, i32imm:$index),
+                 "stw $val, sp[$index]",
+                 [(XCoreStwsp GRRegs:$val, immU16:$index)]>;
+}
 
-let mayLoad=1 in
+let mayLoad=1 in {
 def LDWSP_ru6 : _FRU6<
-                 (outs GRRegs:$dst), (ins MEMii:$b),
+                 (outs GRRegs:$dst), (ins i32imm:$b),
                  "ldw $dst, sp[$b]",
                  []>;
 
 def LDWSP_lru6 : _FLRU6<
-                 (outs GRRegs:$dst), (ins MEMii:$b),
+                 (outs GRRegs:$dst), (ins i32imm:$b),
                  "ldw $dst, sp[$b]",
-                 [(set GRRegs:$dst, (load ADDRspii:$b))]>;
+                 []>;
+}
 
-let neverHasSideEffects = 1 in
+let neverHasSideEffects = 1 in {
 def LDAWSP_ru6 : _FRU6<
-                 (outs GRRegs:$dst), (ins MEMii:$b),
+                 (outs GRRegs:$dst), (ins i32imm:$b),
                  "ldaw $dst, sp[$b]",
                  []>;
 
 def LDAWSP_lru6 : _FLRU6<
-                 (outs GRRegs:$dst), (ins MEMii:$b),
+                 (outs GRRegs:$dst), (ins i32imm:$b),
                  "ldaw $dst, sp[$b]",
-                 [(set GRRegs: $dst, ADDRspii:$b)]>;
+                 []>;
 
-let neverHasSideEffects = 1 in {
 def LDAWSP_ru6_RRegs : _FRU6<
                  (outs RRegs:$dst), (ins i32imm:$b),
                  "ldaw $dst, sp[$b]",
@@ -750,7 +752,7 @@ def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
 // getd, testlcl, tinitlr, getps, setps
 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
                  "bitrev $dst, $src",
-                 []>;
+                 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
 
 def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
                  "byterev $dst, $src",
@@ -762,7 +764,7 @@ def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
 
 // One operand short
 // TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
-// bru, setdp, setcp, setv, setev, kcall, ecallt, ecallf
+// bru, setdp, setcp, setv, setev, kcall
 // dgetreg
 let isBranch=1, isIndirectBranch=1, isTerminator=1 in
 def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
@@ -774,6 +776,16 @@ def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
                  "set sp, $src",
                  []>;
 
+let isBarrier = 1, hasCtrlDep = 1 in 
+def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
+                 "ecallt $src",
+                 []>;
+
+let isBarrier = 1, hasCtrlDep = 1 in 
+def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
+                 "ecallf $src",
+                 []>;
+
 let isCall=1, 
 // All calls clobber the the link register and the non-callee-saved registers:
 Defs = [R0, R1, R2, R3, R11, LR] in {
@@ -790,7 +802,7 @@ def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
 let Defs = [R11] in
 def GETID_0R : _F0R<(outs), (ins),
                  "get r11, id",
-                 []>;
+                 [(set R11, (int_xcore_getid))]>;
 
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
@@ -798,10 +810,6 @@ def GETID_0R : _F0R<(outs), (ins),
 
 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BL_lu10 tglobaladdr:$addr)>;
 def : Pat<(XCoreBranchLink texternalsym:$addr), (BL_lu10 texternalsym:$addr)>;
-def : Pat<(XCoreStwsp GRRegs:$val, immU6:$index),
-          (STWSP_ru6_2 GRRegs:$val, immU6:$index)>;
-def : Pat<(XCoreStwsp GRRegs:$val, immU16:$index),
-          (STWSP_lru6_2 GRRegs:$val, immU16:$index)>;
 
 /// sext_inreg
 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
@@ -852,6 +860,9 @@ def : Pat<(store GRRegs:$val, GRRegs:$addr),
 /// cttz
 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
 
+/// trap
+def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
+
 ///
 /// branch patterns
 ///