using namespace llvm;
-XCoreInstrInfo::XCoreInstrInfo(void)
+XCoreInstrInfo::XCoreInstrInfo()
: TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)),
RI(*this) {
}
return 0;
}
-/// isInvariantLoad - Return true if the specified instruction (which is marked
-/// mayLoad) is loading from a location whose value is invariant across the
-/// function. For example, loading a value from the constant pool or from
-/// from the argument area of a function if it does not change. This should
-/// only return true of *all* loads the instruction does are invariant (if it
-/// does multiple loads).
-bool
-XCoreInstrInfo::isInvariantLoad(const MachineInstr *MI) const {
- // Loads from constants pools and loads from invariant argument slots are
- // invariant
- int Opcode = MI->getOpcode();
- if (Opcode == XCore::LDWCP_ru6 || Opcode == XCore::LDWCP_lru6) {
- return MI->getOperand(1).isCPI();
- }
- int FrameIndex;
- if (isLoadFromStackSlot(MI, FrameIndex)) {
- const MachineFrameInfo &MFI =
- *MI->getParent()->getParent()->getFrameInfo();
- return MFI.isFixedObjectIndex(FrameIndex) &&
- MFI.isImmutableObjectIndex(FrameIndex);
- }
- return false;
-}
-
//===----------------------------------------------------------------------===//
// Branch Analysis
//===----------------------------------------------------------------------===//
static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case XCore::COND_TRUE : return XCore::BRFT_lru6;
case XCore::COND_FALSE : return XCore::BRFF_lru6;
}
static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case XCore::COND_TRUE : return XCore::COND_FALSE;
case XCore::COND_FALSE : return XCore::COND_TRUE;
}
.addImm(0);
}
-void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
- bool isKill, SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const
-{
- LLVM_UNREACHABLE("unimplemented");
-}
-
void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIndex,
.addImm(0);
}
-void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
- SmallVectorImpl<MachineOperand> &Addr,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs) const
-{
- LLVM_UNREACHABLE("unimplemented");
-}
-
bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI) const
return true;
}
-/// BlockHasNoFallThrough - Analyse if MachineBasicBlock does not
-/// fall-through into its successor block.
-bool XCoreInstrInfo::
-BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
-{
- if (MBB.empty()) return false;
-
- switch (MBB.back().getOpcode()) {
- case XCore::RETSP_u6: // Return.
- case XCore::RETSP_lu6:
- case XCore::BAU_1r: // Indirect branch.
- case XCore::BRFU_u6: // Uncond branch.
- case XCore::BRFU_lu6:
- case XCore::BRBU_u6:
- case XCore::BRBU_lu6:
- return true;
- default: return false;
- }
-}
-
/// ReverseBranchCondition - Return the inverse opcode of the
/// specified Branch instruction.
bool XCoreInstrInfo::