Add instruction encodings and disassembly for 1r instructions.

[oota-llvm.git] / lib / Target / XCore / XCoreInstrFormats.td

diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td
index d905a5c6edf1bc1c0f9f3350245afdcd90fc71cb..f7fa673db818d3ddda1f7d16cd7ad4e16e4ce6d0 100644 (file)
--- a/lib/Target/XCore/XCoreInstrFormats.td
+++ b/lib/Target/XCore/XCoreInstrFormats.td
@@ -20,6 +20,7 @@ class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
   let AsmString   = asmstr;
   let Pattern = pattern;
   let Size = sz;
+  field bits<32> SoftFail = 0;
 }
 
 // XCore pseudo instructions format
@@ -84,8 +85,14 @@ class _FL2R<dag outs, dag ins, string asmstr, list<dag> pattern>
     : InstXCore<4, outs, ins, asmstr, pattern> {
 }
 
-class _F1R<dag outs, dag ins, string asmstr, list<dag> pattern>
+class _F1R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
     : InstXCore<2, outs, ins, asmstr, pattern> {
+  bits<4> a;
+
+  let Inst{15-11} = opc{5-1};
+  let Inst{10-5} = 0b111111;
+  let Inst{4} = opc{0};
+  let Inst{3-0} = a;
 }
 
 class _F0R<dag outs, dag ins, string asmstr, list<dag> pattern>