Add support for ISD::TRAP to the XCore backend

[oota-llvm.git] / lib / Target / XCore / XCoreISelLowering.cpp

diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp
index 96b1ae7c5d388256833843e5f014f3ad0e337055..e2d2ab7c89886577cd455a9250564aff23e817ef 100644 (file)
--- a/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/lib/Target/XCore/XCoreISelLowering.cpp
@@ -74,7 +74,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
   setSchedulingPreference(SchedulingForRegPressure);
 
   // Use i32 for setcc operations results (slt, sgt, ...).
-  setSetCCResultContents(ZeroOrOneSetCCResult);
+  setBooleanContents(ZeroOrOneBooleanContent);
 
   // XCore does not have the NodeTypes below.
   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
@@ -88,9 +88,10 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
   
   // 64bit
-  setOperationAction(ISD::ADD, MVT::i64, Custom);
-  setOperationAction(ISD::SUB, MVT::i64, Custom);
-  
+  if (!Subtarget.isXS1A()) {
+    setOperationAction(ISD::ADD, MVT::i64, Custom);
+    setOperationAction(ISD::SUB, MVT::i64, Custom);
+  }
   if (Subtarget.isXS1A()) {
     setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
   }
@@ -105,6 +106,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
   setOperationAction(ISD::ROTL , MVT::i32, Expand);
   setOperationAction(ISD::ROTR , MVT::i32, Expand);
   
+  setOperationAction(ISD::TRAP, MVT::Other, Legal);
+  
   // Expand jump tables for now
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::JumpTable, MVT::i32, Custom);
@@ -160,8 +163,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) {
   case ISD::VASTART:          return LowerVASTART(Op, DAG);
   // FIXME: Remove these when LegalizeDAGTypes lands.
   case ISD::ADD:
-  case ISD::SUB:              return SDValue(ExpandADDSUB(Op.getNode(), DAG),0);
-  
+  case ISD::SUB:              return ExpandADDSUB(Op.getNode(), DAG);
   case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
   default:
     assert(0 && "unimplemented operand");
@@ -169,15 +171,19 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) {
   }
 }
 
-SDNode *XCoreTargetLowering::
-ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
+/// ReplaceNodeResults - Replace the results of node with an illegal result
+/// type with new values built out of custom code.
+void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
+                                             SmallVectorImpl<SDValue>&Results,
+                                             SelectionDAG &DAG) {
   switch (N->getOpcode()) {
-  case ISD::SUB:
-  case ISD::ADD:
-    return ExpandADDSUB(N, DAG);
   default:
-    assert(0 && "Wasn't expecting to be able to lower this!");
-    return NULL;
+    assert(0 && "Don't know how to custom expand this!");
+    return;
+  case ISD::ADD:
+  case ISD::SUB:
+    Results.push_back(ExpandADDSUB(N, DAG));
+    return;
   }
 }
 
@@ -226,9 +232,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
 }
 
 static inline SDValue BuildGetId(SelectionDAG &DAG) {
-  // TODO
-  assert(0 && "Unimplemented");
-  return SDValue();
+  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::i32,
+                     DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
 }
 
 static inline bool isZeroLengthArray(const Type *Ty) {
@@ -296,12 +301,13 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG)
   return DAG.getNode(XCoreISD::DPRelativeWrapper, MVT::i32, JTI);
 }
 
-SDNode *XCoreTargetLowering::
+SDValue XCoreTargetLowering::
 ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
 {
   assert(N->getValueType(0) == MVT::i64 &&
          (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
         "Unknown operand to lower!");
+  assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a");
   
   // Extract components
   SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
@@ -314,18 +320,6 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
                              DAG.getConstant(1, MVT::i32));
   
   // Expand
-  if (Subtarget.isXS1A()) {
-    SDValue Lo = DAG.getNode(N->getOpcode(), MVT::i32, LHSL, RHSL);
-    
-    ISD::CondCode CarryCC = (N->getOpcode() == ISD::ADD) ? ISD::SETULT :
-                                                           ISD::SETUGT;
-    SDValue Carry = DAG.getSetCC(MVT::i32, Lo, LHSL, CarryCC);
-    
-    SDValue Hi = DAG.getNode(N->getOpcode(), MVT::i32, LHSH, Carry);
-    Hi = DAG.getNode(N->getOpcode(), MVT::i32, Hi, RHSH);
-    // Merge the pieces
-    return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
-  }
   unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
                                                    XCoreISD::LSUB;
   SDValue Zero = DAG.getConstant(0, MVT::i32);
@@ -337,7 +331,7 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
                                   LHSH, RHSH, Carry);
   SDValue Hi(Ignored.getNode(), 1);
   // Merge the pieces
-  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
+  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
 }
 
 SDValue XCoreTargetLowering::