if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
TT[4] == '-' && TT[1] - '3' < 6)
return 20;
+ // If the target triple is something non-X86, we don't match.
+ if (!TT.empty()) return 0;
if (M.getEndianness() == Module::LittleEndian &&
M.getPointerSize() == Module::Pointer32)
TT[3] == '6' && TT[4] == '4' && TT[5] == '-')
return 20;
+ // If the target triple is something non-X86-64, we don't match.
+ if (!TT.empty()) return 0;
+
if (M.getEndianness() == Module::LittleEndian &&
M.getPointerSize() == Module::Pointer64)
return 10; // Weak match
/// X86TargetMachine ctor - Create an ILP32 architecture model
///
-X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS, bool is64Bit)
+X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
+ bool is64Bit)
: Subtarget(M, FS, is64Bit),
DataLayout(Subtarget.is64Bit() ?
- std::string("e-p:64:64-d:32:64-l:32:64") :
- std::string("e-p:32:32-d:32:64-l:32:64")),
+ std::string("e-p:64:64-f64:32:64-i64:32:64") :
+ std::string("e-p:32:32-f64:32:64-i64:32:64")),
FrameInfo(TargetFrameInfo::StackGrowsDown,
Subtarget.getStackAlignment(), Subtarget.is64Bit() ? -8 : -4),
InstrInfo(*this), JITInfo(*this), TLInfo(*this) {
return false;
}
-bool X86TargetMachine::addObjectWriter(FunctionPassManager &PM, bool Fast,
- std::ostream &Out) {
- if (Subtarget.isTargetELF()) {
- addX86ELFObjectWriterPass(PM, Out, *this);
- return false;
- }
- return true;
-}
-
bool X86TargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
PM.add(createX86CodeEmitterPass(*this, MCE));
return false;
}
+
+bool X86TargetMachine::addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
+ MachineCodeEmitter &MCE) {
+ PM.add(createX86CodeEmitterPass(*this, MCE));
+ return false;
+}