-//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
+//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// because the register file generator is smart enough to figure out that
// AL aliases AX if we tell it that AX aliased AL (for example).
- // FIXME: X86-64 have different Dwarf numbers.
+ // Dwarf numbering is different for 32-bit and 64-bit, and there are
+ // variations by target as well. Currently the first entry is for X86-64,
+ // second - for X86-32/Darwin and third for X86-32/Linux
+
+ // FIXME: Comments in gcc indicate that Darwin uses different numbering
+ // for debug info and exception handling info:( The numbering here is
+ // for exception handling.
+
// 8-bit registers
// Low registers
- def AL : Register<"AL">, DwarfRegNum<0>;
- def CL : Register<"CL">, DwarfRegNum<1>;
- def DL : Register<"DL">, DwarfRegNum<2>;
- def BL : Register<"BL">, DwarfRegNum<3>;
+ def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
+ def DL : Register<"DL">, DwarfRegNum<[1, 2, 2]>;
+ def CL : Register<"CL">, DwarfRegNum<[2, 1, 1]>;
+ def BL : Register<"BL">, DwarfRegNum<[3, 3, 3]>;
// X86-64 only
- def SIL : Register<"SIL">, DwarfRegNum<4>;
- def DIL : Register<"DIL">, DwarfRegNum<5>;
- def BPL : Register<"BPL">, DwarfRegNum<6>;
- def SPL : Register<"SPL">, DwarfRegNum<7>;
- def R8B : Register<"R8B">, DwarfRegNum<8>;
- def R9B : Register<"R9B">, DwarfRegNum<9>;
- def R10B : Register<"R10B">, DwarfRegNum<10>;
- def R11B : Register<"R11B">, DwarfRegNum<11>;
- def R12B : Register<"R12B">, DwarfRegNum<12>;
- def R13B : Register<"R13B">, DwarfRegNum<13>;
- def R14B : Register<"R14B">, DwarfRegNum<14>;
- def R15B : Register<"R15B">, DwarfRegNum<15>;
+ def SIL : Register<"SIL">, DwarfRegNum<[4, 6, 6]>;
+ def DIL : Register<"DIL">, DwarfRegNum<[5, 7, 7]>;
+ def BPL : Register<"BPL">, DwarfRegNum<[6, 4, 5]>;
+ def SPL : Register<"SPL">, DwarfRegNum<[7, 5, 4]>;
+ def R8B : Register<"R8B">, DwarfRegNum<[8, -2, -2]>;
+ def R9B : Register<"R9B">, DwarfRegNum<[9, -2, -2]>;
+ def R10B : Register<"R10B">, DwarfRegNum<[10, -2, -2]>;
+ def R11B : Register<"R11B">, DwarfRegNum<[11, -2, -2]>;
+ def R12B : Register<"R12B">, DwarfRegNum<[12, -2, -2]>;
+ def R13B : Register<"R13B">, DwarfRegNum<[13, -2, -2]>;
+ def R14B : Register<"R14B">, DwarfRegNum<[14, -2, -2]>;
+ def R15B : Register<"R15B">, DwarfRegNum<[15, -2, -2]>;
// High registers X86-32 only
- def AH : Register<"AH">, DwarfRegNum<0>;
- def CH : Register<"CH">, DwarfRegNum<1>;
- def DH : Register<"DH">, DwarfRegNum<2>;
- def BH : Register<"BH">, DwarfRegNum<3>;
+ def AH : Register<"AH">, DwarfRegNum<[0, 0, 0]>;
+ def DH : Register<"DH">, DwarfRegNum<[1, 2, 2]>;
+ def CH : Register<"CH">, DwarfRegNum<[2, 1, 1]>;
+ def BH : Register<"BH">, DwarfRegNum<[3, 3, 3]>;
// 16-bit registers
- def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<0>;
- def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<1>;
- def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<2>;
- def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<3>;
- def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<4>;
- def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<5>;
- def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<6>;
- def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<7>;
+ def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<[0, 0, 0]>;
+ def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<[1, 2, 2]>;
+ def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<[2, 1, 1]>;
+ def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<[3, 3, 3]>;
+ def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<[4, 6, 6]>;
+ def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<[5, 7, 7]>;
+ def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<[6, 4, 5]>;
+ def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<[7, 5, 4]>;
+ def IP : Register<"IP">, DwarfRegNum<[16]>;
// X86-64 only
- def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
- def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<9>;
- def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<10>;
- def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<11>;
- def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<12>;
- def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<13>;
- def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<14>;
- def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<15>;
+ def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<[8, -2, -2]>;
+ def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<[9, -2, -2]>;
+ def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<[10, -2, -2]>;
+ def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<[11, -2, -2]>;
+ def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<[12, -2, -2]>;
+ def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<[13, -2, -2]>;
+ def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<[14, -2, -2]>;
+ def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<[15, -2, -2]>;
// 32-bit registers
- def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<0>;
- def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<1>;
- def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<2>;
- def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<3>;
- def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<4>;
- def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<5>;
- def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<6>;
- def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<7>;
+ def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<[0, 0, 0]>;
+ def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<[1, 2, 2]>;
+ def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<[2, 1, 1]>;
+ def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<[3, 3, 3]>;
+ def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<[4, 6, 6]>;
+ def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<[5, 7, 7]>;
+ def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<[6, 4, 5]>;
+ def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<[7, 5, 4]>;
+ def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<[16, 8, 8]>;
// X86-64 only
- def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
- def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<9>;
- def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<10>;
- def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<11>;
- def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<12>;
- def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<13>;
- def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<14>;
- def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<15>;
+ def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<[8, -2, -2]>;
+ def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<[9, -2, -2]>;
+ def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<[10, -2, -2]>;
+ def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<[11, -2, -2]>;
+ def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<[12, -2, -2]>;
+ def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<[13, -2, -2]>;
+ def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<[14, -2, -2]>;
+ def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<[15, -2, -2]>;
// 64-bit registers, X86-64 only
- def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<0>;
- def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<1>;
- def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<2>;
- def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<3>;
- def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<4>;
- def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<5>;
- def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<6>;
- def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<7>;
-
- def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<8>;
- def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<9>;
- def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<10>;
- def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<11>;
- def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<12>;
- def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>;
- def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>;
- def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>;
+ def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<[0, -2, -2]>;
+ def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<[1, -2, -2]>;
+ def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<[2, -2, -2]>;
+ def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<[3, -2, -2]>;
+ def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<[4, -2, -2]>;
+ def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<[5, -2, -2]>;
+ def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<[6, -2, -2]>;
+ def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<[7, -2, -2]>;
+
+ def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
+ def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
+ def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
+ def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
+ def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
+ def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
+ def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
+ def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
+ def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<[16, -2, -2]>;
// MMX Registers. These are actually aliased to ST0 .. ST7
- def MM0 : Register<"MM0">, DwarfRegNum<29>;
- def MM1 : Register<"MM1">, DwarfRegNum<30>;
- def MM2 : Register<"MM2">, DwarfRegNum<31>;
- def MM3 : Register<"MM3">, DwarfRegNum<32>;
- def MM4 : Register<"MM4">, DwarfRegNum<33>;
- def MM5 : Register<"MM5">, DwarfRegNum<34>;
- def MM6 : Register<"MM6">, DwarfRegNum<35>;
- def MM7 : Register<"MM7">, DwarfRegNum<36>;
+ def MM0 : Register<"MM0">, DwarfRegNum<[41, 29, 29]>;
+ def MM1 : Register<"MM1">, DwarfRegNum<[42, 30, 30]>;
+ def MM2 : Register<"MM2">, DwarfRegNum<[43, 31, 31]>;
+ def MM3 : Register<"MM3">, DwarfRegNum<[44, 32, 32]>;
+ def MM4 : Register<"MM4">, DwarfRegNum<[45, 33, 33]>;
+ def MM5 : Register<"MM5">, DwarfRegNum<[46, 34, 34]>;
+ def MM6 : Register<"MM6">, DwarfRegNum<[47, 35, 35]>;
+ def MM7 : Register<"MM7">, DwarfRegNum<[48, 36, 36]>;
// Pseudo Floating Point registers
- def FP0 : Register<"FP0">, DwarfRegNum<-1>;
- def FP1 : Register<"FP1">, DwarfRegNum<-1>;
- def FP2 : Register<"FP2">, DwarfRegNum<-1>;
- def FP3 : Register<"FP3">, DwarfRegNum<-1>;
- def FP4 : Register<"FP4">, DwarfRegNum<-1>;
- def FP5 : Register<"FP5">, DwarfRegNum<-1>;
- def FP6 : Register<"FP6">, DwarfRegNum<-1>;
+ def FP0 : Register<"FP0">;
+ def FP1 : Register<"FP1">;
+ def FP2 : Register<"FP2">;
+ def FP3 : Register<"FP3">;
+ def FP4 : Register<"FP4">;
+ def FP5 : Register<"FP5">;
+ def FP6 : Register<"FP6">;
// XMM Registers, used by the various SSE instruction set extensions
- def XMM0: Register<"XMM0">, DwarfRegNum<17>;
- def XMM1: Register<"XMM1">, DwarfRegNum<18>;
- def XMM2: Register<"XMM2">, DwarfRegNum<19>;
- def XMM3: Register<"XMM3">, DwarfRegNum<20>;
- def XMM4: Register<"XMM4">, DwarfRegNum<21>;
- def XMM5: Register<"XMM5">, DwarfRegNum<22>;
- def XMM6: Register<"XMM6">, DwarfRegNum<23>;
- def XMM7: Register<"XMM7">, DwarfRegNum<24>;
+ def XMM0: Register<"XMM0">, DwarfRegNum<[17, 21, 21]>;
+ def XMM1: Register<"XMM1">, DwarfRegNum<[18, 22, 22]>;
+ def XMM2: Register<"XMM2">, DwarfRegNum<[19, 23, 23]>;
+ def XMM3: Register<"XMM3">, DwarfRegNum<[20, 24, 24]>;
+ def XMM4: Register<"XMM4">, DwarfRegNum<[21, 25, 25]>;
+ def XMM5: Register<"XMM5">, DwarfRegNum<[22, 26, 26]>;
+ def XMM6: Register<"XMM6">, DwarfRegNum<[23, 27, 27]>;
+ def XMM7: Register<"XMM7">, DwarfRegNum<[24, 28, 28]>;
// X86-64 only
- def XMM8: Register<"XMM8">, DwarfRegNum<25>;
- def XMM9: Register<"XMM9">, DwarfRegNum<26>;
- def XMM10: Register<"XMM10">, DwarfRegNum<27>;
- def XMM11: Register<"XMM11">, DwarfRegNum<28>;
- def XMM12: Register<"XMM12">, DwarfRegNum<29>;
- def XMM13: Register<"XMM13">, DwarfRegNum<30>;
- def XMM14: Register<"XMM14">, DwarfRegNum<31>;
- def XMM15: Register<"XMM15">, DwarfRegNum<32>;
+ def XMM8: Register<"XMM8">, DwarfRegNum<[25, -2, -2]>;
+ def XMM9: Register<"XMM9">, DwarfRegNum<[26, -2, -2]>;
+ def XMM10: Register<"XMM10">, DwarfRegNum<[27, -2, -2]>;
+ def XMM11: Register<"XMM11">, DwarfRegNum<[28, -2, -2]>;
+ def XMM12: Register<"XMM12">, DwarfRegNum<[29, -2, -2]>;
+ def XMM13: Register<"XMM13">, DwarfRegNum<[30, -2, -2]>;
+ def XMM14: Register<"XMM14">, DwarfRegNum<[31, -2, -2]>;
+ def XMM15: Register<"XMM15">, DwarfRegNum<[32, -2, -2]>;
// Floating point stack registers
- def ST0 : Register<"ST(0)">, DwarfRegNum<11>;
- def ST1 : Register<"ST(1)">, DwarfRegNum<12>;
- def ST2 : Register<"ST(2)">, DwarfRegNum<13>;
- def ST3 : Register<"ST(3)">, DwarfRegNum<14>;
- def ST4 : Register<"ST(4)">, DwarfRegNum<15>;
- def ST5 : Register<"ST(5)">, DwarfRegNum<16>;
- def ST6 : Register<"ST(6)">, DwarfRegNum<17>;
- def ST7 : Register<"ST(7)">, DwarfRegNum<18>;
+ def ST0 : Register<"ST(0)">, DwarfRegNum<[33, 12, 11]>;
+ def ST1 : Register<"ST(1)">, DwarfRegNum<[34, 13, 12]>;
+ def ST2 : Register<"ST(2)">, DwarfRegNum<[35, 14, 13]>;
+ def ST3 : Register<"ST(3)">, DwarfRegNum<[36, 15, 14]>;
+ def ST4 : Register<"ST(4)">, DwarfRegNum<[37, 16, 15]>;
+ def ST5 : Register<"ST(5)">, DwarfRegNum<[38, 17, 16]>;
+ def ST6 : Register<"ST(6)">, DwarfRegNum<[39, 18, 17]>;
+ def ST7 : Register<"ST(7)">, DwarfRegNum<[40, 19, 18]>;
+
+ // Status flags register
+ def EFLAGS : Register<"EFLAGS">;
}
+
+//===----------------------------------------------------------------------===//
+// Subregister Set Definitions... now that we have all of the pieces, define the
+// sub registers for each register.
+//
+
+def : SubRegSet<1, [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+// It's unclear if this subreg set is safe, given that not all registers
+// in the class have an 'H' subreg.
+// def : SubRegSet<2, [AX, CX, DX, BX],
+// [AH, CH, DH, BH]>;
+
+def : SubRegSet<1, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<2, [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
+ [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+
+def : SubRegSet<1, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [AL, CL, DL, BL, SPL, BPL, SIL, DIL,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def : SubRegSet<2, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [AX, CX, DX, BX, SP, BP, SI, DI,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
+
+def : SubRegSet<3, [RAX, RCX, RDX, RBX, RSP, RBP, RSI, RDI,
+ R8, R9, R10, R11, R12, R13, R14, R15],
+ [EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI,
+ R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]>;
+
//===----------------------------------------------------------------------===//
// Register Class Definitions... now that we have all of the pieces, define the
// top-level register classes. The order specified in the register list is
def GR16 : RegisterClass<"X86", [i16], 16,
[AX, CX, DX, SI, DI, BX, BP, SP,
R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
+ let SubRegClassList = [GR8];
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
def GR32 : RegisterClass<"X86", [i32], 32,
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
+ let SubRegClassList = [GR8, GR16];
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
def GR64 : RegisterClass<"X86", [i64], 64,
[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
RBX, R14, R15, R12, R13, RBP, RSP]> {
+ let SubRegClassList = [GR8, GR16, GR32];
let MethodProtos = [{
iterator allocation_order_end(const MachineFunction &MF) const;
}];
}
-// GR16, GR32 subclasses which contain registers that have R8 sub-registers.
+// GR16, GR32 subclasses which contain registers that have GR8 sub-registers.
// These should only be used for 32-bit mode.
-def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>;
-def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>;
+def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
+ let SubRegClassList = [GR8];
+}
+def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
+ let SubRegClassList = [GR8, GR16];
+}
// Scalar SSE2 floating point registers.
def FR32 : RegisterClass<"X86", [f32], 32,
// faster on common hardware. In reality, this should be controlled by a
// command line option or something.
-def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
+def RFP32 : RegisterClass<"X86", [f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
+def RFP64 : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
+def RFP80 : RegisterClass<"X86", [f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
// Floating point stack registers (these are not allocatable by the
// register allocator - the floating point stackifier is responsible
}
}];
}
+
+// Status flags registers.
+def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
+ let CopyCost = -1; // Don't allow copying of status registers.
+}
projects / oota-llvm.git / blobdiff