Opc = X86::MOVSSmr;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDmr;
- } else if (RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSmr;
- } else if (RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDmr;
} else {
assert(0 && "Unknown regclass");
Opc = X86::MOVSSrm;
} else if (RC == &X86::FR64RegClass) {
Opc = X86::MOVSDrm;
- } else if (RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSrm;
- } else if (RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDrm;
} else {
assert(0 && "Unknown regclass");
Opc = X86::MOV16rr;
} else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
Opc = X86::FpMOV;
- } else if (RC == &X86::FR32RegClass || RC == &X86::V4F4RegClass) {
+ } else if (RC == &X86::FR32RegClass) {
+ Opc = X86::FsMOVAPSrr;
+ } else if (RC == &X86::FR64RegClass) {
+ Opc = X86::FsMOVAPDrr;
+ } else if (RC == &X86::V4F32RegClass) {
Opc = X86::MOVAPSrr;
- } else if (RC == &X86::FR64RegClass || RC == &X86::V2F8RegClass) {
+ } else if (RC == &X86::V2F64RegClass) {
Opc = X86::MOVAPDrr;
} else {
assert(0 && "Unknown regclass");
.addZImm(MI->getOperand(1).getImmedValue());
else if (MI->getOperand(1).isGlobalAddress())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
- .addGlobalAddress(MI->getOperand(1).getGlobal());
+ .addGlobalAddress(MI->getOperand(1).getGlobal(),
+ false, MI->getOperand(1).getOffset());
assert(0 && "Unknown operand for MakeMI!");
return 0;
}
case X86::ADD8rr: return MakeMRInst(X86::ADD8mr , FrameIndex, MI);
case X86::ADD16rr: return MakeMRInst(X86::ADD16mr, FrameIndex, MI);
case X86::ADD32rr: return MakeMRInst(X86::ADD32mr, FrameIndex, MI);
- case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
- case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
case X86::ADD8ri: return MakeMIInst(X86::ADD8mi , FrameIndex, MI);
case X86::ADD16ri: return MakeMIInst(X86::ADD16mi, FrameIndex, MI);
case X86::ADD32ri: return MakeMIInst(X86::ADD32mi, FrameIndex, MI);
+ case X86::ADD16ri8: return MakeMIInst(X86::ADD16mi8,FrameIndex, MI);
+ case X86::ADD32ri8: return MakeMIInst(X86::ADD32mi8,FrameIndex, MI);
+ case X86::ADC32rr: return MakeMRInst(X86::ADC32mr, FrameIndex, MI);
+ case X86::ADC32ri: return MakeMIInst(X86::ADC32mi, FrameIndex, MI);
+ case X86::ADC32ri8: return MakeMIInst(X86::ADC32mi8,FrameIndex, MI);
case X86::SUB8rr: return MakeMRInst(X86::SUB8mr , FrameIndex, MI);
case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
- case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
- case X86::SBB8ri: return MakeMIInst(X86::SBB8mi, FrameIndex, MI);
- case X86::SBB16ri: return MakeMIInst(X86::SBB16mi, FrameIndex, MI);
- case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
case X86::SUB32ri: return MakeMIInst(X86::SUB32mi, FrameIndex, MI);
+ case X86::SUB16ri8: return MakeMIInst(X86::SUB16mi8,FrameIndex, MI);
+ case X86::SUB32ri8: return MakeMIInst(X86::SUB32mi8,FrameIndex, MI);
+ case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
+ case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
+ case X86::SBB32ri8: return MakeMIInst(X86::SBB32mi8,FrameIndex, MI);
case X86::AND8rr: return MakeMRInst(X86::AND8mr , FrameIndex, MI);
case X86::AND16rr: return MakeMRInst(X86::AND16mr, FrameIndex, MI);
case X86::AND32rr: return MakeMRInst(X86::AND32mr, FrameIndex, MI);
case X86::AND8ri: return MakeMIInst(X86::AND8mi , FrameIndex, MI);
case X86::AND16ri: return MakeMIInst(X86::AND16mi, FrameIndex, MI);
case X86::AND32ri: return MakeMIInst(X86::AND32mi, FrameIndex, MI);
+ case X86::AND16ri8: return MakeMIInst(X86::AND16mi8,FrameIndex, MI);
+ case X86::AND32ri8: return MakeMIInst(X86::AND32mi8,FrameIndex, MI);
case X86::OR8rr: return MakeMRInst(X86::OR8mr , FrameIndex, MI);
case X86::OR16rr: return MakeMRInst(X86::OR16mr, FrameIndex, MI);
case X86::OR32rr: return MakeMRInst(X86::OR32mr, FrameIndex, MI);
case X86::OR8ri: return MakeMIInst(X86::OR8mi , FrameIndex, MI);
case X86::OR16ri: return MakeMIInst(X86::OR16mi, FrameIndex, MI);
case X86::OR32ri: return MakeMIInst(X86::OR32mi, FrameIndex, MI);
+ case X86::OR16ri8: return MakeMIInst(X86::OR16mi8, FrameIndex, MI);
+ case X86::OR32ri8: return MakeMIInst(X86::OR32mi8, FrameIndex, MI);
case X86::XOR8rr: return MakeMRInst(X86::XOR8mr , FrameIndex, MI);
case X86::XOR16rr: return MakeMRInst(X86::XOR16mr, FrameIndex, MI);
case X86::XOR32rr: return MakeMRInst(X86::XOR32mr, FrameIndex, MI);
case X86::XOR8ri: return MakeMIInst(X86::XOR8mi , FrameIndex, MI);
case X86::XOR16ri: return MakeMIInst(X86::XOR16mi, FrameIndex, MI);
case X86::XOR32ri: return MakeMIInst(X86::XOR32mi, FrameIndex, MI);
+ case X86::XOR16ri8: return MakeMIInst(X86::XOR16mi8,FrameIndex, MI);
+ case X86::XOR32ri8: return MakeMIInst(X86::XOR32mi8,FrameIndex, MI);
case X86::SHL8rCL: return MakeMInst( X86::SHL8mCL ,FrameIndex, MI);
case X86::SHL16rCL: return MakeMInst( X86::SHL16mCL,FrameIndex, MI);
case X86::SHL32rCL: return MakeMInst( X86::SHL32mCL,FrameIndex, MI);
case X86::CMP8ri: return MakeMIInst(X86::CMP8mi , FrameIndex, MI);
case X86::CMP16ri: return MakeMIInst(X86::CMP16mi, FrameIndex, MI);
case X86::CMP32ri: return MakeMIInst(X86::CMP32mi, FrameIndex, MI);
+ // Alias scalar SSE instructions
+ case X86::FsMOVAPSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
+ case X86::FsMOVAPDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
// Scalar SSE instructions
case X86::MOVSSrr: return MakeMRInst(X86::MOVSSmr, FrameIndex, MI);
case X86::MOVSDrr: return MakeMRInst(X86::MOVSDmr, FrameIndex, MI);
case X86::IMUL32rr: return MakeRMInst(X86::IMUL32rm,FrameIndex, MI);
case X86::IMUL16rri: return MakeRMIInst(X86::IMUL16rmi, FrameIndex, MI);
case X86::IMUL32rri: return MakeRMIInst(X86::IMUL32rmi, FrameIndex, MI);
+ case X86::IMUL16rri8:return MakeRMIInst(X86::IMUL16rmi8, FrameIndex, MI);
+ case X86::IMUL32rri8:return MakeRMIInst(X86::IMUL32rmi8, FrameIndex, MI);
case X86::CMP8rr: return MakeRMInst(X86::CMP8rm , FrameIndex, MI);
case X86::CMP16rr: return MakeRMInst(X86::CMP16rm, FrameIndex, MI);
case X86::CMP32rr: return MakeRMInst(X86::CMP32rm, FrameIndex, MI);
case X86::MOVZX16rr8:return MakeRMInst(X86::MOVZX16rm8 , FrameIndex, MI);
case X86::MOVZX32rr8:return MakeRMInst(X86::MOVZX32rm8, FrameIndex, MI);
case X86::MOVZX32rr16:return MakeRMInst(X86::MOVZX32rm16, FrameIndex, MI);
+ // Alias scalar SSE instructions
+ case X86::FsMOVAPSrr:return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
+ case X86::FsMOVAPDrr:return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);
// Scalar SSE instructions
case X86::MOVSSrr: return MakeRMInst(X86::MOVSSrm, FrameIndex, MI);
case X86::MOVSDrr: return MakeRMInst(X86::MOVSDrm, FrameIndex, MI);