// X86 specific DAG Nodes.
//
-def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>,
- SDTCisSameAs<1, 2>]>;
+def SDTIntShiftDOp: SDTypeProfile<1, 3,
+ [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
+ SDTCisInt<0>, SDTCisInt<3>]>;
-def SDTX86Cmov : SDTypeProfile<1, 4,
+def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
+
+def SDTX86Cmov : SDTypeProfile<1, 3,
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
- SDTCisVT<3, OtherVT>, SDTCisVT<4, FlagVT>]>;
+ SDTCisVT<3, i8>]>;
+
+def SDTX86BrCond : SDTypeProfile<0, 2,
+ [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
+
+def SDTX86SetCC : SDTypeProfile<1, 1,
+ [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
+
+def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
+
+def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
+ SDTCisVT<1, i32> ]>;
+
+def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+
+def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
+
+def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
+
+def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
+
+def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
+def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
+
+def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
+ [SDNPOutFlag]>;
+def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest,
+ [SDNPOutFlag]>;
+
+def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
+ [SDNPInFlag, SDNPOutFlag]>;
+def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
+ [SDNPHasChain, SDNPInFlag]>;
+def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
+ [SDNPInFlag, SDNPOutFlag]>;
+
+def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
+ [SDNPHasChain, SDNPOptInFlag]>;
+
+def X86callseq_start :
+ SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
+ [SDNPHasChain]>;
+def X86callseq_end :
+ SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
+ [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+
+def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
+ [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
-def SDTX86BrCond : SDTypeProfile<0, 3,
- [SDTCisVT<0, OtherVT>,
- SDTCisVT<1, OtherVT>, SDTCisVT<2, FlagVT>]>;
+def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
+ [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
+ [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
-def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest, []>;
-def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest, []>;
+def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
+ [SDNPHasChain, SDNPOutFlag]>;
-def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov, []>;
-def X86Brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, [SDNPHasChain]>;
+def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
//===----------------------------------------------------------------------===//
// X86 Operand Definitions.
def i16mem : X86MemOperand<"printi16mem">;
def i32mem : X86MemOperand<"printi32mem">;
def i64mem : X86MemOperand<"printi64mem">;
+def i128mem : X86MemOperand<"printi128mem">;
def f32mem : X86MemOperand<"printf32mem">;
def f64mem : X86MemOperand<"printf64mem">;
-def f80mem : X86MemOperand<"printf80mem">;
+def f128mem : X86MemOperand<"printf128mem">;
def SSECC : Operand<i8> {
let PrintMethod = "printSSECC";
}
+def piclabel: Operand<i32> {
+ let PrintMethod = "printPICLabel";
+}
+
// A couple of more descriptive operand definitions.
// 16-bits but only 8 bits are significant.
def i16i8imm : Operand<i16>;
// 32-bits but only 8 bits are significant.
def i32i8imm : Operand<i32>;
-// PCRelative calls need special operand formatting.
-let PrintMethod = "printCallOperand" in
- def calltarget : Operand<i32>;
-
// Branch targets have OtherVT type.
def brtarget : Operand<OtherVT>;
// Define X86 specific addressing mode.
def addr : ComplexPattern<i32, 4, "SelectAddr", []>;
def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr",
- [add,
- frameindex, constpool, globaladdr, externalsym]>;
+ [add, mul, shl, frameindex]>;
//===----------------------------------------------------------------------===//
// X86 Instruction Format Definitions.
// Format specifies the encoding used by the instruction. This is part of the
// ad-hoc solution used to emit machine instruction encodings by our machine
// code emitter.
-class Format<bits<5> val> {
- bits<5> Value = val;
+class Format<bits<6> val> {
+ bits<6> Value = val;
}
def Pseudo : Format<0>; def RawFrm : Format<1>;
def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
def MRM6m : Format<30>; def MRM7m : Format<31>;
+def MRMInitReg : Format<32>;
+
+//===----------------------------------------------------------------------===//
+// X86 Instruction Predicate Definitions.
+def HasMMX : Predicate<"Subtarget->hasMMX()">;
+def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
+def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
+def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
+def FPStack : Predicate<"!Subtarget->hasSSE2()">;
//===----------------------------------------------------------------------===//
// X86 specific pattern fragments.
bits<8> Opcode = opcod;
Format Form = f;
- bits<5> FormBits = Form.Value;
+ bits<6> FormBits = Form.Value;
ImmType ImmT = i;
bits<2> ImmTypeBits = ImmT.Value;
//===----------------------------------------------------------------------===//
// Pattern fragments...
//
+
+// X86 specific condition code. These correspond to CondCode in
+// X86ISelLowering.h. They must be kept in synch.
+def X86_COND_A : PatLeaf<(i8 0)>;
+def X86_COND_AE : PatLeaf<(i8 1)>;
+def X86_COND_B : PatLeaf<(i8 2)>;
+def X86_COND_BE : PatLeaf<(i8 3)>;
+def X86_COND_E : PatLeaf<(i8 4)>;
+def X86_COND_G : PatLeaf<(i8 5)>;
+def X86_COND_GE : PatLeaf<(i8 6)>;
+def X86_COND_L : PatLeaf<(i8 7)>;
+def X86_COND_LE : PatLeaf<(i8 8)>;
+def X86_COND_NE : PatLeaf<(i8 9)>;
+def X86_COND_NO : PatLeaf<(i8 10)>;
+def X86_COND_NP : PatLeaf<(i8 11)>;
+def X86_COND_NS : PatLeaf<(i8 12)>;
+def X86_COND_O : PatLeaf<(i8 13)>;
+def X86_COND_P : PatLeaf<(i8 14)>;
+def X86_COND_S : PatLeaf<(i8 15)>;
+
def i16immSExt8 : PatLeaf<(i16 imm), [{
// i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
// sign extended field.
def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
+def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
+def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
+
def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>;
def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>;
def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>;
def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>;
def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>;
+def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextload node:$ptr, i1))>;
def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>;
def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>;
def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>;
def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>;
def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
-def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
-
+def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extload node:$ptr, i1))>;
//===----------------------------------------------------------------------===//
// Instruction templates...
// Instruction list...
//
-def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node.
-def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // nop
-
-def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", []>;
+def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
+ [(X86callseq_start imm:$amt)]>;
def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
- "#ADJCALLSTACKUP", []>;
+ "#ADJCALLSTACKUP",
+ [(X86callseq_end imm:$amt1, imm:$amt2)]>;
def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
-let isTerminator = 1 in
- let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
- def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
+def IMPLICIT_DEF_R8 : I<0, Pseudo, (ops R8:$dst),
+ "#IMPLICIT_DEF $dst",
+ [(set R8:$dst, (undef))]>;
+def IMPLICIT_DEF_R16 : I<0, Pseudo, (ops R16:$dst),
+ "#IMPLICIT_DEF $dst",
+ [(set R16:$dst, (undef))]>;
+def IMPLICIT_DEF_R32 : I<0, Pseudo, (ops R32:$dst),
+ "#IMPLICIT_DEF $dst",
+ [(set R32:$dst, (undef))]>;
+
+// Nop
+def NOOP : I<0x90, RawFrm, (ops), "nop", []>;
//===----------------------------------------------------------------------===//
// Control Flow Instructions...
//
// Return instructions.
-let isTerminator = 1, isReturn = 1, isBarrier = 1 in
- def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
-let isTerminator = 1, isReturn = 1, isBarrier = 1 in
- def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
+let isTerminator = 1, isReturn = 1, isBarrier = 1,
+ hasCtrlDep = 1, noResults = 1 in {
+ def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>;
+ def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt",
+ [(X86retflag imm:$amt)]>;
+}
// All branches are RawFrm, Void, Branch, and Terminators
-let isBranch = 1, isTerminator = 1 in
+let isBranch = 1, isTerminator = 1, noResults = 1 in
class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
I<opcode, RawFrm, ops, asm, pattern>;
+// Conditional branches
let isBarrier = 1 in
def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
- [(X86Brcond bb:$dst, SETEQ, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_E)]>, TB;
def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
- [(X86Brcond bb:$dst, SETNE, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
- [(X86Brcond bb:$dst, SETLT, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_L)]>, TB;
def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
- [(X86Brcond bb:$dst, SETLE, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
- [(X86Brcond bb:$dst, SETGT, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_G)]>, TB;
def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
- [(X86Brcond bb:$dst, SETGE, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
- [(X86Brcond bb:$dst, SETULT, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_B)]>, TB;
def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst",
- [(X86Brcond bb:$dst, SETULE, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst",
- [(X86Brcond bb:$dst, SETUGT, STATUS)]>, Imp<[STATUS],[]>, TB;
+ [(X86brcond bb:$dst, X86_COND_A)]>, TB;
def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst",
- [(X86Brcond bb:$dst, SETUGE, STATUS)]>, Imp<[STATUS],[]>, TB;
-
-def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", []>, TB;
-def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", []>, TB;
-def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", []>, TB;
-def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", []>, TB;
+ [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
+
+def JS : IBr<0x88, (ops brtarget:$dst), "js $dst",
+ [(X86brcond bb:$dst, X86_COND_S)]>, TB;
+def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst",
+ [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
+def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst",
+ [(X86brcond bb:$dst, X86_COND_P)]>, TB;
+def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst",
+ [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
+def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst",
+ [(X86brcond bb:$dst, X86_COND_O)]>, TB;
+def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
+ [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
//===----------------------------------------------------------------------===//
// Call Instructions...
//
-let isCall = 1 in
+let isCall = 1, noResults = 1 in
// All calls clobber the non-callee saved registers...
let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
- def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", []>;
- def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", []>;
- def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>;
+ def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst), "call ${dst:call}",
+ []>;
+ def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst",
+ [(X86call R32:$dst)]>;
+ def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst",
+ [(X86call (loadi32 addr:$dst))]>;
}
// Tail call stuff.
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
- def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL", []>;
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
+ def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL", []>;
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>;
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
"jmp {*}$dst # TAIL CALL", []>;
def POP32r : I<0x58, AddRegFrm,
(ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
+def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label),
+ "call $label", []>;
+
let isTwoAddress = 1 in // R32 = bswap R32
def BSWAP32r : I<0xC8, AddRegFrm,
- (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB;
+ (ops R32:$dst, R32:$src),
+ "bswap{l} $dst",
+ [(set R32:$dst, (bswap R32:$src))]>, TB;
def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
(ops R8:$src1, R8:$src2),
"lea{l} {$src|$dst}, {$dst|$src}",
[(set R32:$dst, leaaddr:$src)]>;
-def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", []>,
+def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}",
+ [(X86rep_movs i8)]>,
Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
-def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", []>,
+def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}",
+ [(X86rep_movs i16)]>,
Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
-def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", []>,
+def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}",
+ [(X86rep_movs i32)]>,
Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
-def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", []>,
+def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}",
+ [(X86rep_stos i8)]>,
Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
-def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", []>,
+def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}",
+ [(X86rep_stos i16)]>,
Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
-def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>,
+def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}",
+ [(X86rep_stos i32)]>,
Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
//
def IN8rr : I<0xEC, RawFrm, (ops),
"in{b} {%dx, %al|%AL, %DX}",
- [(set AL, (readport DX))]>, Imp<[DX], [AL]>;
+ []>, Imp<[DX], [AL]>;
def IN16rr : I<0xED, RawFrm, (ops),
"in{w} {%dx, %ax|%AX, %DX}",
- [(set AX, (readport DX))]>, Imp<[DX], [AX]>, OpSize;
+ []>, Imp<[DX], [AX]>, OpSize;
def IN32rr : I<0xED, RawFrm, (ops),
"in{l} {%dx, %eax|%EAX, %DX}",
- [(set EAX, (readport DX))]>, Imp<[DX],[EAX]>;
+ []>, Imp<[DX],[EAX]>;
def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
"in{b} {$port, %al|%AL, $port}",
- [(set AL, (readport i16immZExt8:$port))]>,
+ []>,
Imp<[], [AL]>;
def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
"in{w} {$port, %ax|%AX, $port}",
- [(set AX, (readport i16immZExt8:$port))]>,
+ []>,
Imp<[], [AX]>, OpSize;
def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
"in{l} {$port, %eax|%EAX, $port}",
- [(set EAX, (readport i16immZExt8:$port))]>,
+ []>,
Imp<[],[EAX]>;
def OUT8rr : I<0xEE, RawFrm, (ops),
"out{b} {%al, %dx|%DX, %AL}",
- [(writeport AL, DX)]>, Imp<[DX, AL], []>;
+ []>, Imp<[DX, AL], []>;
def OUT16rr : I<0xEF, RawFrm, (ops),
"out{w} {%ax, %dx|%DX, %AX}",
- [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize;
+ []>, Imp<[DX, AX], []>, OpSize;
def OUT32rr : I<0xEF, RawFrm, (ops),
"out{l} {%eax, %dx|%DX, %EAX}",
- [(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
+ []>, Imp<[DX, EAX], []>;
def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
"out{b} {%al, $port|$port, %AL}",
- [(writeport AL, i16immZExt8:$port)]>,
+ []>,
Imp<[AL], []>;
def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
"out{w} {%ax, $port|$port, %AX}",
- [(writeport AX, i16immZExt8:$port)]>,
+ []>,
Imp<[AX], []>, OpSize;
def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
"out{l} {%eax, $port|$port, %EAX}",
- [(writeport EAX, i16immZExt8:$port)]>,
+ []>,
Imp<[EAX], []>;
//===----------------------------------------------------------------------===//
//
// Extra precision multiplication
-def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", []>,
+def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src",
+ // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
+ // This probably ought to be moved to a def : Pat<> if the
+ // syntax can be accepted.
+ [(set AL, (mul AL, R8:$src))]>,
Imp<[AL],[AX]>; // AL,AH = AL*R8
def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>,
Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>,
Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
- "mul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
+ "mul{b} $src",
+ // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
+ // This probably ought to be moved to a def : Pat<> if the
+ // syntax can be accepted.
+ [(set AL, (mul AL, (loadi8 addr:$src)))]>,
+ Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
"mul{w} $src", []>, Imp<[AX],[AX,DX]>,
OpSize; // AX,DX = AX*[mem16]
(ops R16:$dst, R16:$src1, R16:$src2),
"cmovb {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETULT, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_B))]>,
+ TB, OpSize;
def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmovb {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETULT, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_B))]>,
+ TB, OpSize;
def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmovb {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETULT, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_B))]>,
+ TB;
def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmovb {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETULT, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_B))]>,
+ TB;
def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmovae {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETUGE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_AE))]>,
+ TB, OpSize;
def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmovae {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETUGE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_AE))]>,
+ TB, OpSize;
def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmovae {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETUGE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_AE))]>,
+ TB;
def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmovae {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETUGE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_AE))]>,
+ TB;
def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmove {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETEQ, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_E))]>,
+ TB, OpSize;
def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmove {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETEQ, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_E))]>,
+ TB, OpSize;
def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmove {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETEQ, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_E))]>,
+ TB;
def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmove {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETEQ, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_E))]>,
+ TB;
def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmovne {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETNE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_NE))]>,
+ TB, OpSize;
def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmovne {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETNE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_NE))]>,
+ TB, OpSize;
def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmovne {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETNE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_NE))]>,
+ TB;
def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmovne {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETNE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_NE))]>,
+ TB;
def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmovbe {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETULE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_BE))]>,
+ TB, OpSize;
def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmovbe {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETULE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_BE))]>,
+ TB, OpSize;
def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmovbe {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETULE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_BE))]>,
+ TB;
def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmovbe {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETULE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_BE))]>,
+ TB;
def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmova {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETUGT, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_A))]>,
+ TB, OpSize;
def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmova {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETUGT, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_A))]>,
+ TB, OpSize;
def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmova {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETUGT, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_A))]>,
+ TB;
def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmova {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETUGT, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_A))]>,
+ TB;
def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmovl {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETLT, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_L))]>,
+ TB, OpSize;
def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmovl {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETLT, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_L))]>,
+ TB, OpSize;
def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmovl {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETLT, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_L))]>,
+ TB;
def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmovl {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETLT, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_L))]>,
+ TB;
def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmovge {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETGE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_GE))]>,
+ TB, OpSize;
def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmovge {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETGE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_GE))]>,
+ TB, OpSize;
def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmovge {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETGE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_GE))]>,
+ TB;
def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmovge {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETGE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_GE))]>,
+ TB;
def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmovle {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETLE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_LE))]>,
+ TB, OpSize;
def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmovle {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETLE, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_LE))]>,
+ TB, OpSize;
def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmovle {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETLE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_LE))]>,
+ TB;
def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmovle {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETLE, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_LE))]>,
+ TB;
def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
"cmovg {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
- SETGT, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_G))]>,
+ TB, OpSize;
def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
"cmovg {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
- SETGT, STATUS))]>,
- Imp<[STATUS],[]>, TB, OpSize;
+ X86_COND_G))]>,
+ TB, OpSize;
def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
"cmovg {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
- SETGT, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_G))]>,
+ TB;
def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
"cmovg {$src2, $dst|$dst, $src2}",
[(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
- SETGT, STATUS))]>,
- Imp<[STATUS],[]>, TB;
+ X86_COND_G))]>,
+ TB;
def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
- "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+ "cmovs {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
+ X86_COND_S))]>,
+ TB, OpSize;
def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+ "cmovs {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
+ X86_COND_S))]>,
+ TB, OpSize;
def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
- "cmovs {$src2, $dst|$dst, $src2}", []>, TB;
+ "cmovs {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
+ X86_COND_S))]>,
+ TB;
def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovs {$src2, $dst|$dst, $src2}", []>, TB;
+ "cmovs {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
+ X86_COND_S))]>,
+ TB;
def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
- "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+ "cmovns {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
+ X86_COND_NS))]>,
+ TB, OpSize;
def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+ "cmovns {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
+ X86_COND_NS))]>,
+ TB, OpSize;
def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
- "cmovns {$src2, $dst|$dst, $src2}", []>, TB;
+ "cmovns {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
+ X86_COND_NS))]>,
+ TB;
def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovns {$src2, $dst|$dst, $src2}", []>, TB;
+ "cmovns {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
+ X86_COND_NS))]>,
+ TB;
def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
- "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+ "cmovp {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
+ X86_COND_P))]>,
+ TB, OpSize;
def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+ "cmovp {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
+ X86_COND_P))]>,
+ TB, OpSize;
def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
- "cmovp {$src2, $dst|$dst, $src2}", []>, TB;
+ "cmovp {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
+ X86_COND_P))]>,
+ TB;
def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovp {$src2, $dst|$dst, $src2}", []>, TB;
+ "cmovp {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
+ X86_COND_P))]>,
+ TB;
def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16
(ops R16:$dst, R16:$src1, R16:$src2),
- "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+ "cmovnp {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (X86cmov R16:$src1, R16:$src2,
+ X86_COND_NP))]>,
+ TB, OpSize;
def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16]
(ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+ "cmovnp {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (X86cmov R16:$src1, (loadi16 addr:$src2),
+ X86_COND_NP))]>,
+ TB, OpSize;
def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32
(ops R32:$dst, R32:$src1, R32:$src2),
- "cmovnp {$src2, $dst|$dst, $src2}", []>, TB;
+ "cmovnp {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, R32:$src2,
+ X86_COND_NP))]>,
+ TB;
def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32]
(ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovnp {$src2, $dst|$dst, $src2}", []>, TB;
+ "cmovnp {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, (loadi32 addr:$src2),
+ X86_COND_NP))]>,
+ TB;
// unary instructions
def AND32mi8 : Ii8<0x83, MRM4m,
(ops i32mem:$dst, i32i8imm :$src),
"and{l} {$src, $dst|$dst, $src}",
- [(store (add (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
+ [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
}
}
// Shift instructions
-// FIXME: provide shorter instructions when imm8 == 1
def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
// Rotate instructions
// FIXME: provide shorter instructions when imm8 == 1
def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src),
- "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+ "rol{b} {%cl, $dst|$dst, %CL}",
+ [(set R8:$dst, (rotl R8:$src, CL))]>, Imp<[CL],[]>;
def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src),
- "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
+ "rol{w} {%cl, $dst|$dst, %CL}",
+ [(set R16:$dst, (rotl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src),
- "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+ "rol{l} {%cl, $dst|$dst, %CL}",
+ [(set R32:$dst, (rotl R32:$src, CL))]>, Imp<[CL],[]>;
def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
- "rol{b} {$src2, $dst|$dst, $src2}", []>;
+ "rol{b} {$src2, $dst|$dst, $src2}",
+ [(set R8:$dst, (rotl R8:$src1, (i8 imm:$src2)))]>;
def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "rol{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
+ "rol{w} {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (rotl R16:$src1, (i8 imm:$src2)))]>, OpSize;
def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "rol{l} {$src2, $dst|$dst, $src2}", []>;
+ "rol{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (rotl R32:$src1, (i8 imm:$src2)))]>;
let isTwoAddress = 0 in {
def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
- "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+ "rol{b} {%cl, $dst|$dst, %CL}",
+ [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
+ Imp<[CL],[]>;
def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
- "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
+ "rol{w} {%cl, $dst|$dst, %CL}",
+ [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
+ Imp<[CL],[]>, OpSize;
def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
- "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+ "rol{l} {%cl, $dst|$dst, %CL}",
+ [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
+ Imp<[CL],[]>;
def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
- "rol{b} {$src, $dst|$dst, $src}", []>;
+ "rol{b} {$src, $dst|$dst, $src}",
+ [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
- "rol{w} {$src, $dst|$dst, $src}", []>, OpSize;
+ "rol{w} {$src, $dst|$dst, $src}",
+ [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
+ OpSize;
def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
- "rol{l} {$src, $dst|$dst, $src}", []>;
+ "rol{l} {$src, $dst|$dst, $src}",
+ [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
}
def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src),
- "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+ "ror{b} {%cl, $dst|$dst, %CL}",
+ [(set R8:$dst, (rotr R8:$src, CL))]>, Imp<[CL],[]>;
def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src),
- "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
+ "ror{w} {%cl, $dst|$dst, %CL}",
+ [(set R16:$dst, (rotr R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src),
- "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+ "ror{l} {%cl, $dst|$dst, %CL}",
+ [(set R32:$dst, (rotr R32:$src, CL))]>, Imp<[CL],[]>;
def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
- "ror{b} {$src2, $dst|$dst, $src2}", []>;
+ "ror{b} {$src2, $dst|$dst, $src2}",
+ [(set R8:$dst, (rotr R8:$src1, (i8 imm:$src2)))]>;
def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "ror{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
+ "ror{w} {$src2, $dst|$dst, $src2}",
+ [(set R16:$dst, (rotr R16:$src1, (i8 imm:$src2)))]>, OpSize;
def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "ror{l} {$src2, $dst|$dst, $src2}", []>;
+ "ror{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (rotr R32:$src1, (i8 imm:$src2)))]>;
let isTwoAddress = 0 in {
def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
- "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+ "ror{b} {%cl, $dst|$dst, %CL}",
+ [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
+ Imp<[CL],[]>;
def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
- "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
+ "ror{w} {%cl, $dst|$dst, %CL}",
+ [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
+ Imp<[CL],[]>, OpSize;
def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
- "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
+ "ror{l} {%cl, $dst|$dst, %CL}",
+ [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
+ Imp<[CL],[]>;
def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
- "ror{b} {$src, $dst|$dst, $src}", []>;
+ "ror{b} {$src, $dst|$dst, $src}",
+ [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
- "ror{w} {$src, $dst|$dst, $src}", []>, OpSize;
+ "ror{w} {$src, $dst|$dst, $src}",
+ [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
+ OpSize;
def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
- "ror{l} {$src, $dst|$dst, $src}", []>;
+ "ror{l} {$src, $dst|$dst, $src}",
+ [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
}
// Double shift instructions (generalizations of rotate)
-
def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+ "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(set R32:$dst, (X86shld R32:$src1, R32:$src2, CL))]>,
Imp<[CL],[]>, TB;
def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+ "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(set R32:$dst, (X86shrd R32:$src1, R32:$src2, CL))]>,
Imp<[CL],[]>, TB;
def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
- "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+ "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(set R16:$dst, (X86shld R16:$src1, R16:$src2, CL))]>,
Imp<[CL],[]>, TB, OpSize;
def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
- "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+ "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(set R16:$dst, (X86shrd R16:$src1, R16:$src2, CL))]>,
Imp<[CL],[]>, TB, OpSize;
let isCommutable = 1 in { // These instructions commute to each other.
def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
(ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
- "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB;
+ "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set R32:$dst, (X86shld R32:$src1, R32:$src2,
+ (i8 imm:$src3)))]>,
+ TB;
def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
(ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
- "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB;
+ "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set R32:$dst, (X86shrd R32:$src1, R32:$src2,
+ (i8 imm:$src3)))]>,
+ TB;
def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
(ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
- "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set R16:$dst, (X86shld R16:$src1, R16:$src2,
+ (i8 imm:$src3)))]>,
TB, OpSize;
def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
(ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
- "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set R16:$dst, (X86shrd R16:$src1, R16:$src2,
+ (i8 imm:$src3)))]>,
TB, OpSize;
}
let isTwoAddress = 0 in {
def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+ "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(store (X86shld (loadi32 addr:$dst), R32:$src2, CL),
+ addr:$dst)]>,
Imp<[CL],[]>, TB;
def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+ "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(store (X86shrd (loadi32 addr:$dst), R32:$src2, CL),
+ addr:$dst)]>,
Imp<[CL],[]>, TB;
def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
(ops i32mem:$dst, R32:$src2, i8imm:$src3),
- "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(store (X86shld (loadi32 addr:$dst), R32:$src2,
+ (i8 imm:$src3)), addr:$dst)]>,
TB;
def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
(ops i32mem:$dst, R32:$src2, i8imm:$src3),
- "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(store (X86shrd (loadi32 addr:$dst), R32:$src2,
+ (i8 imm:$src3)), addr:$dst)]>,
TB;
def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2),
- "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+ "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(store (X86shld (loadi16 addr:$dst), R16:$src2, CL),
+ addr:$dst)]>,
Imp<[CL],[]>, TB, OpSize;
def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2),
- "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
+ "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(store (X86shrd (loadi16 addr:$dst), R16:$src2, CL),
+ addr:$dst)]>,
Imp<[CL],[]>, TB, OpSize;
def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
(ops i16mem:$dst, R16:$src2, i8imm:$src3),
- "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(store (X86shld (loadi16 addr:$dst), R16:$src2,
+ (i8 imm:$src3)), addr:$dst)]>,
TB, OpSize;
def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
(ops i16mem:$dst, R16:$src2, i8imm:$src3),
- "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(store (X86shrd (loadi16 addr:$dst), R16:$src2,
+ (i8 imm:$src3)), addr:$dst)]>,
TB, OpSize;
}
[(set R32:$dst, (add R32:$src1, imm:$src2))]>;
}
-// FIXME: move ADD16ri8 above ADD16ri to optimize for space.
def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
"add{w} {$src2, $dst|$dst, $src2}",
[(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>,
let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
+ "adc{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (adde R32:$src1, R32:$src2))]>;
}
def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
+ "adc{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (adde R32:$src1, (load addr:$src2)))]>;
def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
-def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
+ "adc{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (adde R32:$src1, imm:$src2))]>;
+def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
+ "adc{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (adde R32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in {
def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
+ "adc{l} {$src2, $dst|$dst, $src2}",
+ [(store (adde (load addr:$dst), R32:$src2), addr:$dst)]>;
def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
- def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
+ "adc{l} {$src2, $dst|$dst, $src2}",
+ [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
+ def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2),
+ "adc{l} {$src2, $dst|$dst, $src2}",
+ [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
}
def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
+ "sbb{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (sube R32:$src1, R32:$src2))]>;
let isTwoAddress = 0 in {
def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
+ "sbb{l} {$src2, $dst|$dst, $src2}",
+ [(store (sube (load addr:$dst), R32:$src2), addr:$dst)]>;
def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
- "sbb{b} {$src2, $dst|$dst, $src2}", []>;
- def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
+ "sbb{b} {$src2, $dst|$dst, $src2}",
+ [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
- def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
- def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
+ "sbb{l} {$src2, $dst|$dst, $src2}",
+ [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
+ def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
+ "sbb{l} {$src2, $dst|$dst, $src2}",
+ [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
-def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
- "sbb{b} {$src2, $dst|$dst, $src2}", []>;
-def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
-
def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
+ "sbb{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (sube R32:$src1, (load addr:$src2)))]>;
def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
-
-def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
-def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
+ "sbb{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (sube R32:$src1, imm:$src2))]>;
+def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
+ "sbb{l} {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (sube R32:$src1, i32immSExt8:$src2))]>;
let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
"test{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R8:$src1, R8:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86test R8:$src1, R8:$src2)]>;
def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
"test{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R16:$src1, R16:$src2))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86test R16:$src1, R16:$src2)]>, OpSize;
def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
"test{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R32:$src1, R32:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86test R32:$src1, R32:$src2)]>;
}
def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
"test{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test (loadi8 addr:$src1), R8:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86test (loadi8 addr:$src1), R8:$src2)]>;
def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
"test{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test (loadi16 addr:$src1), R16:$src2))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86test (loadi16 addr:$src1), R16:$src2)]>,
+ OpSize;
def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
"test{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test (loadi32 addr:$src1), R32:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86test (loadi32 addr:$src1), R32:$src2)]>;
def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
"test{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R8:$src1, (loadi8 addr:$src2)))]>,
- Imp<[],[STATUS]>;
+ [(X86test R8:$src1, (loadi8 addr:$src2))]>;
def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
"test{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R16:$src1, (loadi16 addr:$src2)))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86test R16:$src1, (loadi16 addr:$src2))]>,
+ OpSize;
def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
"test{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R32:$src1, (loadi32 addr:$src2)))]>,
- Imp<[],[STATUS]>;
+ [(X86test R32:$src1, (loadi32 addr:$src2))]>;
def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
(ops R8:$src1, i8imm:$src2),
"test{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R8:$src1, imm:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86test R8:$src1, imm:$src2)]>;
def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
(ops R16:$src1, i16imm:$src2),
"test{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R16:$src1, imm:$src2))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86test R16:$src1, imm:$src2)]>, OpSize;
def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
(ops R32:$src1, i32imm:$src2),
"test{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test R32:$src1, imm:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86test R32:$src1, imm:$src2)]>;
def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
(ops i8mem:$src1, i8imm:$src2),
"test{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test (loadi8 addr:$src1), imm:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86test (loadi8 addr:$src1), imm:$src2)]>;
def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
(ops i16mem:$src1, i16imm:$src2),
"test{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test (loadi16 addr:$src1), imm:$src2))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86test (loadi16 addr:$src1), imm:$src2)]>,
+ OpSize;
def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
(ops i32mem:$src1, i32imm:$src2),
"test{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86test (loadi32 addr:$src1), imm:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86test (loadi32 addr:$src1), imm:$src2)]>;
// Condition code ops, incl. set if equal/not equal/...
def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
-def SETBr : I<0x92, MRM0r,
- (ops R8 :$dst), "setb $dst", []>, TB; // R8 = < unsign
-def SETBm : I<0x92, MRM0m,
- (ops i8mem:$dst), "setb $dst", []>, TB; // [mem8] = < unsign
-def SETAEr : I<0x93, MRM0r,
- (ops R8 :$dst), "setae $dst", []>, TB; // R8 = >= unsign
-def SETAEm : I<0x93, MRM0m,
- (ops i8mem:$dst), "setae $dst", []>, TB; // [mem8] = >= unsign
def SETEr : I<0x94, MRM0r,
- (ops R8 :$dst), "sete $dst", []>, TB; // R8 = ==
+ (ops R8 :$dst),
+ "sete $dst",
+ [(set R8:$dst, (X86setcc X86_COND_E))]>,
+ TB; // R8 = ==
def SETEm : I<0x94, MRM0m,
- (ops i8mem:$dst), "sete $dst", []>, TB; // [mem8] = ==
+ (ops i8mem:$dst),
+ "sete $dst",
+ [(store (X86setcc X86_COND_E), addr:$dst)]>,
+ TB; // [mem8] = ==
def SETNEr : I<0x95, MRM0r,
- (ops R8 :$dst), "setne $dst", []>, TB; // R8 = !=
+ (ops R8 :$dst),
+ "setne $dst",
+ [(set R8:$dst, (X86setcc X86_COND_NE))]>,
+ TB; // R8 = !=
def SETNEm : I<0x95, MRM0m,
- (ops i8mem:$dst), "setne $dst", []>, TB; // [mem8] = !=
+ (ops i8mem:$dst),
+ "setne $dst",
+ [(store (X86setcc X86_COND_NE), addr:$dst)]>,
+ TB; // [mem8] = !=
+def SETLr : I<0x9C, MRM0r,
+ (ops R8 :$dst),
+ "setl $dst",
+ [(set R8:$dst, (X86setcc X86_COND_L))]>,
+ TB; // R8 = < signed
+def SETLm : I<0x9C, MRM0m,
+ (ops i8mem:$dst),
+ "setl $dst",
+ [(store (X86setcc X86_COND_L), addr:$dst)]>,
+ TB; // [mem8] = < signed
+def SETGEr : I<0x9D, MRM0r,
+ (ops R8 :$dst),
+ "setge $dst",
+ [(set R8:$dst, (X86setcc X86_COND_GE))]>,
+ TB; // R8 = >= signed
+def SETGEm : I<0x9D, MRM0m,
+ (ops i8mem:$dst),
+ "setge $dst",
+ [(store (X86setcc X86_COND_GE), addr:$dst)]>,
+ TB; // [mem8] = >= signed
+def SETLEr : I<0x9E, MRM0r,
+ (ops R8 :$dst),
+ "setle $dst",
+ [(set R8:$dst, (X86setcc X86_COND_LE))]>,
+ TB; // R8 = <= signed
+def SETLEm : I<0x9E, MRM0m,
+ (ops i8mem:$dst),
+ "setle $dst",
+ [(store (X86setcc X86_COND_LE), addr:$dst)]>,
+ TB; // [mem8] = <= signed
+def SETGr : I<0x9F, MRM0r,
+ (ops R8 :$dst),
+ "setg $dst",
+ [(set R8:$dst, (X86setcc X86_COND_G))]>,
+ TB; // R8 = > signed
+def SETGm : I<0x9F, MRM0m,
+ (ops i8mem:$dst),
+ "setg $dst",
+ [(store (X86setcc X86_COND_G), addr:$dst)]>,
+ TB; // [mem8] = > signed
+
+def SETBr : I<0x92, MRM0r,
+ (ops R8 :$dst),
+ "setb $dst",
+ [(set R8:$dst, (X86setcc X86_COND_B))]>,
+ TB; // R8 = < unsign
+def SETBm : I<0x92, MRM0m,
+ (ops i8mem:$dst),
+ "setb $dst",
+ [(store (X86setcc X86_COND_B), addr:$dst)]>,
+ TB; // [mem8] = < unsign
+def SETAEr : I<0x93, MRM0r,
+ (ops R8 :$dst),
+ "setae $dst",
+ [(set R8:$dst, (X86setcc X86_COND_AE))]>,
+ TB; // R8 = >= unsign
+def SETAEm : I<0x93, MRM0m,
+ (ops i8mem:$dst),
+ "setae $dst",
+ [(store (X86setcc X86_COND_AE), addr:$dst)]>,
+ TB; // [mem8] = >= unsign
def SETBEr : I<0x96, MRM0r,
- (ops R8 :$dst), "setbe $dst", []>, TB; // R8 = <= unsign
+ (ops R8 :$dst),
+ "setbe $dst",
+ [(set R8:$dst, (X86setcc X86_COND_BE))]>,
+ TB; // R8 = <= unsign
def SETBEm : I<0x96, MRM0m,
- (ops i8mem:$dst), "setbe $dst", []>, TB; // [mem8] = <= unsign
+ (ops i8mem:$dst),
+ "setbe $dst",
+ [(store (X86setcc X86_COND_BE), addr:$dst)]>,
+ TB; // [mem8] = <= unsign
def SETAr : I<0x97, MRM0r,
- (ops R8 :$dst), "seta $dst", []>, TB; // R8 = > signed
+ (ops R8 :$dst),
+ "seta $dst",
+ [(set R8:$dst, (X86setcc X86_COND_A))]>,
+ TB; // R8 = > signed
def SETAm : I<0x97, MRM0m,
- (ops i8mem:$dst), "seta $dst", []>, TB; // [mem8] = > signed
+ (ops i8mem:$dst),
+ "seta $dst",
+ [(store (X86setcc X86_COND_A), addr:$dst)]>,
+ TB; // [mem8] = > signed
+
def SETSr : I<0x98, MRM0r,
- (ops R8 :$dst), "sets $dst", []>, TB; // R8 = <sign bit>
+ (ops R8 :$dst),
+ "sets $dst",
+ [(set R8:$dst, (X86setcc X86_COND_S))]>,
+ TB; // R8 = <sign bit>
def SETSm : I<0x98, MRM0m,
- (ops i8mem:$dst), "sets $dst", []>, TB; // [mem8] = <sign bit>
+ (ops i8mem:$dst),
+ "sets $dst",
+ [(store (X86setcc X86_COND_S), addr:$dst)]>,
+ TB; // [mem8] = <sign bit>
def SETNSr : I<0x99, MRM0r,
- (ops R8 :$dst), "setns $dst", []>, TB; // R8 = !<sign bit>
+ (ops R8 :$dst),
+ "setns $dst",
+ [(set R8:$dst, (X86setcc X86_COND_NS))]>,
+ TB; // R8 = !<sign bit>
def SETNSm : I<0x99, MRM0m,
- (ops i8mem:$dst), "setns $dst", []>, TB; // [mem8] = !<sign bit>
+ (ops i8mem:$dst),
+ "setns $dst",
+ [(store (X86setcc X86_COND_NS), addr:$dst)]>,
+ TB; // [mem8] = !<sign bit>
def SETPr : I<0x9A, MRM0r,
- (ops R8 :$dst), "setp $dst", []>, TB; // R8 = parity
+ (ops R8 :$dst),
+ "setp $dst",
+ [(set R8:$dst, (X86setcc X86_COND_P))]>,
+ TB; // R8 = parity
def SETPm : I<0x9A, MRM0m,
- (ops i8mem:$dst), "setp $dst", []>, TB; // [mem8] = parity
+ (ops i8mem:$dst),
+ "setp $dst",
+ [(store (X86setcc X86_COND_P), addr:$dst)]>,
+ TB; // [mem8] = parity
def SETNPr : I<0x9B, MRM0r,
- (ops R8 :$dst), "setnp $dst", []>, TB; // R8 = not parity
+ (ops R8 :$dst),
+ "setnp $dst",
+ [(set R8:$dst, (X86setcc X86_COND_NP))]>,
+ TB; // R8 = not parity
def SETNPm : I<0x9B, MRM0m,
- (ops i8mem:$dst), "setnp $dst", []>, TB; // [mem8] = not parity
-def SETLr : I<0x9C, MRM0r,
- (ops R8 :$dst), "setl $dst", []>, TB; // R8 = < signed
-def SETLm : I<0x9C, MRM0m,
- (ops i8mem:$dst), "setl $dst", []>, TB; // [mem8] = < signed
-def SETGEr : I<0x9D, MRM0r,
- (ops R8 :$dst), "setge $dst", []>, TB; // R8 = >= signed
-def SETGEm : I<0x9D, MRM0m,
- (ops i8mem:$dst), "setge $dst", []>, TB; // [mem8] = >= signed
-def SETLEr : I<0x9E, MRM0r,
- (ops R8 :$dst), "setle $dst", []>, TB; // R8 = <= signed
-def SETLEm : I<0x9E, MRM0m,
- (ops i8mem:$dst), "setle $dst", []>, TB; // [mem8] = <= signed
-def SETGr : I<0x9F, MRM0r,
- (ops R8 :$dst), "setg $dst", []>, TB; // R8 = < signed
-def SETGm : I<0x9F, MRM0m,
- (ops i8mem:$dst), "setg $dst", []>, TB; // [mem8] = < signed
+ (ops i8mem:$dst),
+ "setnp $dst",
+ [(store (X86setcc X86_COND_NP), addr:$dst)]>,
+ TB; // [mem8] = not parity
// Integer comparisons
def CMP8rr : I<0x38, MRMDestReg,
(ops R8 :$src1, R8 :$src2),
"cmp{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R8:$src1, R8:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp R8:$src1, R8:$src2)]>;
def CMP16rr : I<0x39, MRMDestReg,
(ops R16:$src1, R16:$src2),
"cmp{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R16:$src1, R16:$src2))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86cmp R16:$src1, R16:$src2)]>, OpSize;
def CMP32rr : I<0x39, MRMDestReg,
(ops R32:$src1, R32:$src2),
"cmp{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R32:$src1, R32:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp R32:$src1, R32:$src2)]>;
def CMP8mr : I<0x38, MRMDestMem,
(ops i8mem :$src1, R8 :$src2),
"cmp{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp (loadi8 addr:$src1), R8:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp (loadi8 addr:$src1), R8:$src2)]>;
def CMP16mr : I<0x39, MRMDestMem,
(ops i16mem:$src1, R16:$src2),
"cmp{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp (loadi16 addr:$src1), R16:$src2))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86cmp (loadi16 addr:$src1), R16:$src2)]>, OpSize;
def CMP32mr : I<0x39, MRMDestMem,
(ops i32mem:$src1, R32:$src2),
"cmp{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp (loadi32 addr:$src1), R32:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp (loadi32 addr:$src1), R32:$src2)]>;
def CMP8rm : I<0x3A, MRMSrcMem,
(ops R8 :$src1, i8mem :$src2),
"cmp{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R8:$src1, (loadi8 addr:$src2)))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp R8:$src1, (loadi8 addr:$src2))]>;
def CMP16rm : I<0x3B, MRMSrcMem,
(ops R16:$src1, i16mem:$src2),
"cmp{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R16:$src1, (loadi16 addr:$src2)))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86cmp R16:$src1, (loadi16 addr:$src2))]>, OpSize;
def CMP32rm : I<0x3B, MRMSrcMem,
(ops R32:$src1, i32mem:$src2),
"cmp{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R32:$src1, (loadi32 addr:$src2)))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp R32:$src1, (loadi32 addr:$src2))]>;
def CMP8ri : Ii8<0x80, MRM7r,
(ops R8:$src1, i8imm:$src2),
"cmp{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R8:$src1, imm:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp R8:$src1, imm:$src2)]>;
def CMP16ri : Ii16<0x81, MRM7r,
(ops R16:$src1, i16imm:$src2),
"cmp{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R16:$src1, imm:$src2))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86cmp R16:$src1, imm:$src2)]>, OpSize;
def CMP32ri : Ii32<0x81, MRM7r,
(ops R32:$src1, i32imm:$src2),
"cmp{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp R32:$src1, imm:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp R32:$src1, imm:$src2)]>;
def CMP8mi : Ii8 <0x80, MRM7m,
(ops i8mem :$src1, i8imm :$src2),
"cmp{b} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
def CMP16mi : Ii16<0x81, MRM7m,
(ops i16mem:$src1, i16imm:$src2),
"cmp{w} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
- Imp<[],[STATUS]>, OpSize;
+ [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
def CMP32mi : Ii32<0x81, MRM7m,
(ops i32mem:$src1, i32imm:$src2),
"cmp{l} {$src2, $src1|$src1, $src2}",
- [(set STATUS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>,
- Imp<[],[STATUS]>;
+ [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
// Sign/Zero extenders
def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src),
"movz{wl|x} {$src, $dst|$dst, $src}",
[(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB;
-// Handling 1 bit zextload and sextload
-def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
-def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
-def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
-def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
+//===----------------------------------------------------------------------===//
+// Miscellaneous Instructions
+//===----------------------------------------------------------------------===//
+
+def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
+ TB, Imp<[],[EAX,EDX]>;
-// Handling 1 bit extload
-def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
+//===----------------------------------------------------------------------===//
+// Alias Instructions
+//===----------------------------------------------------------------------===//
-// Modeling anyext as zext
+// Alias instructions that map movr0 to xor.
+// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
+def MOV8r0 : I<0x30, MRMInitReg, (ops R8 :$dst),
+ "xor{b} $dst, $dst",
+ [(set R8:$dst, 0)]>;
+def MOV16r0 : I<0x31, MRMInitReg, (ops R16:$dst),
+ "xor{w} $dst, $dst",
+ [(set R16:$dst, 0)]>, OpSize;
+def MOV32r0 : I<0x31, MRMInitReg, (ops R32:$dst),
+ "xor{l} $dst, $dst",
+ [(set R32:$dst, 0)]>;
+
+//===----------------------------------------------------------------------===//
+// DWARF Pseudo Instructions
+//
+
+def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
+ "; .loc $file, $line, $col",
+ [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
+ (i32 imm:$file))]>;
+
+def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
+ "\nLdebug_loc${id:debug}:",
+ [(dwarf_label (i32 imm:$id))]>;
+
+//===----------------------------------------------------------------------===//
+// Non-Instruction Patterns
+//===----------------------------------------------------------------------===//
+
+// ConstantPool GlobalAddress, ExternalSymbol
+def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
+def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
+def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
+
+def : Pat<(add R32:$src1, (X86Wrapper tconstpool:$src2)),
+ (ADD32ri R32:$src1, tconstpool:$src2)>;
+def : Pat<(add R32:$src1, (X86Wrapper tglobaladdr :$src2)),
+ (ADD32ri R32:$src1, tglobaladdr:$src2)>;
+def : Pat<(add R32:$src1, (X86Wrapper texternalsym:$src2)),
+ (ADD32ri R32:$src1, texternalsym:$src2)>;
+
+def : Pat<(store (X86Wrapper tconstpool:$src), addr:$dst),
+ (MOV32mi addr:$dst, tconstpool:$src)>;
+def : Pat<(store (X86Wrapper tglobaladdr:$src), addr:$dst),
+ (MOV32mi addr:$dst, tglobaladdr:$src)>;
+def : Pat<(store (X86Wrapper texternalsym:$src), addr:$dst),
+ (MOV32mi addr:$dst, texternalsym:$src)>;
+
+// Calls
+def : Pat<(X86call tglobaladdr:$dst),
+ (CALLpcrel32 tglobaladdr:$dst)>;
+def : Pat<(X86call texternalsym:$dst),
+ (CALLpcrel32 texternalsym:$dst)>;
+
+// X86 specific add which produces a flag.
+def : Pat<(addc R32:$src1, R32:$src2),
+ (ADD32rr R32:$src1, R32:$src2)>;
+def : Pat<(addc R32:$src1, (load addr:$src2)),
+ (ADD32rm R32:$src1, addr:$src2)>;
+def : Pat<(addc R32:$src1, imm:$src2),
+ (ADD32ri R32:$src1, imm:$src2)>;
+def : Pat<(addc R32:$src1, i32immSExt8:$src2),
+ (ADD32ri8 R32:$src1, i32immSExt8:$src2)>;
+
+def : Pat<(subc R32:$src1, R32:$src2),
+ (SUB32rr R32:$src1, R32:$src2)>;
+def : Pat<(subc R32:$src1, (load addr:$src2)),
+ (SUB32rm R32:$src1, addr:$src2)>;
+def : Pat<(subc R32:$src1, imm:$src2),
+ (SUB32ri R32:$src1, imm:$src2)>;
+def : Pat<(subc R32:$src1, i32immSExt8:$src2),
+ (SUB32ri8 R32:$src1, i32immSExt8:$src2)>;
+
+def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1),
+ (MOV8mi addr:$dst, imm:$src)>;
+def : Pat<(truncstore R8:$src, addr:$dst, i1),
+ (MOV8mr addr:$dst, R8:$src)>;
+
+// {s|z}extload bool -> {s|z}extload byte
+def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
+def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
+def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
+def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
+def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
+
+// extload bool -> extload byte
+def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
+
+// anyext -> zext
def : Pat<(i16 (anyext R8 :$src)), (MOVZX16rr8 R8 :$src)>;
def : Pat<(i32 (anyext R8 :$src)), (MOVZX32rr8 R8 :$src)>;
def : Pat<(i32 (anyext R16:$src)), (MOVZX32rr16 R16:$src)>;
//===----------------------------------------------------------------------===//
-// XMM Floating point support (requires SSE2)
+// Some peepholes
//===----------------------------------------------------------------------===//
-def MOVSSrr : I<0x10, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
- "movss {$src, $dst|$dst, $src}", []>, XS;
-def MOVSSrm : I<0x10, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
- "movss {$src, $dst|$dst, $src}", []>, XS;
-def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, V4F4:$src),
- "movss {$src, $dst|$dst, $src}", []>, XS;
-def MOVSDrr : I<0x10, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
- "movsd {$src, $dst|$dst, $src}", []>, XD;
-def MOVSDrm : I<0x10, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
- "movsd {$src, $dst|$dst, $src}", []>, XD;
-def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, V2F8:$src),
- "movsd {$src, $dst|$dst, $src}", []>, XD;
-
-def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V2F8:$src),
- "cvttsd2si {$src, $dst|$dst, $src}",
- [(set R32:$dst, (fp_to_sint V2F8:$src))]>, XD;
-def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
- "cvttsd2si {$src, $dst|$dst, $src}", []>, XD;
-def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V4F4:$src),
- "cvttss2si {$src, $dst|$dst, $src}",
- [(set R32:$dst, (fp_to_sint V4F4:$src))]>, XS;
-def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
- "cvttss2si {$src, $dst|$dst, $src}", []>, XS;
-def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops V4F4:$dst, V2F8:$src),
- "cvtsd2ss {$src, $dst|$dst, $src}",
- [(set V4F4:$dst, (fround V2F8:$src))]>, XS;
-def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops V4F4:$dst, f64mem:$src),
- "cvtsd2ss {$src, $dst|$dst, $src}", []>, XS;
-def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops V2F8:$dst, V4F4:$src),
- "cvtss2sd {$src, $dst|$dst, $src}",
- [(set V2F8:$dst, (fextend V4F4:$src))]>, XD;
-def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops V2F8:$dst, f32mem:$src),
- "cvtss2sd {$src, $dst|$dst, $src}", []>, XD;
-def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops V4F4:$dst, R32:$src),
- "cvtsi2ss {$src, $dst|$dst, $src}",
- [(set V4F4:$dst, (sint_to_fp R32:$src))]>, XS;
-def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops V4F4:$dst, i32mem:$src),
- "cvtsi2ss {$src, $dst|$dst, $src}", []>, XS;
-def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops V2F8:$dst, R32:$src),
- "cvtsi2sd {$src, $dst|$dst, $src}",
- [(set V2F8:$dst, (sint_to_fp R32:$src))]>, XD;
-def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops V2F8:$dst, i32mem:$src),
- "cvtsi2sd {$src, $dst|$dst, $src}", []>, XD;
-
-def SQRTSSrm : I<0x51, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
- "sqrtss {$src, $dst|$dst, $src}", []>, XS;
-def SQRTSSrr : I<0x51, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
- "sqrtss {$src, $dst|$dst, $src}",
- [(set V4F4:$dst, (fsqrt V4F4:$src))]>, XS;
-def SQRTSDrm : I<0x51, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
- "sqrtsd {$src, $dst|$dst, $src}", []>, XD;
-def SQRTSDrr : I<0x51, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
- "sqrtsd {$src, $dst|$dst, $src}",
- [(set V2F8:$dst, (fsqrt V2F8:$src))]>, XD;
-
-def UCOMISDrr: I<0x2E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
- "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize;
-def UCOMISDrm: I<0x2E, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
- "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize;
-def UCOMISSrr: I<0x2E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
- "ucomiss {$src, $dst|$dst, $src}", []>, TB;
-def UCOMISSrm: I<0x2E, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
- "ucomiss {$src, $dst|$dst, $src}", []>, TB;
-
-// Pseudo-instructions that map fld0 to xorps/xorpd for sse.
-// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def FLD0SS : I<0x57, MRMSrcReg, (ops V4F4:$dst),
- "xorps $dst, $dst", []>, TB;
-def FLD0SD : I<0x57, MRMSrcReg, (ops V2F8:$dst),
- "xorpd $dst, $dst", []>, TB, OpSize;
+// (shl x, 1) ==> (add x, x)
+def : Pat<(shl R8 :$src1, (i8 1)), (ADD8rr R8 :$src1, R8 :$src1)>;
+def : Pat<(shl R16:$src1, (i8 1)), (ADD16rr R16:$src1, R16:$src1)>;
+def : Pat<(shl R32:$src1, (i8 1)), (ADD32rr R32:$src1, R32:$src1)>;
-let isTwoAddress = 1 in {
-let isCommutable = 1 in {
-def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "addss {$src2, $dst|$dst, $src2}",
- [(set V4F4:$dst, (fadd V4F4:$src1, V4F4:$src2))]>, XS;
-def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "addsd {$src2, $dst|$dst, $src2}",
- [(set V2F8:$dst, (fadd V2F8:$src1, V2F8:$src2))]>, XD;
-def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "andps {$src2, $dst|$dst, $src2}", []>, TB;
-def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "andpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "mulss {$src2, $dst|$dst, $src2}",
- [(set V4F4:$dst, (fmul V4F4:$src1, V4F4:$src2))]>, XS;
-def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "mulsd {$src2, $dst|$dst, $src2}",
- [(set V2F8:$dst, (fmul V2F8:$src1, V2F8:$src2))]>, XD;
-def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "orps {$src2, $dst|$dst, $src2}", []>, TB;
-def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "orpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "xorps {$src2, $dst|$dst, $src2}", []>, TB;
-def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "xorpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-}
-def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "andnps {$src2, $dst|$dst, $src2}", []>, TB;
-def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "andnpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
- "addss {$src2, $dst|$dst, $src2}", []>, XS;
-def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
- "addsd {$src2, $dst|$dst, $src2}", []>, XD;
-def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
- "mulss {$src2, $dst|$dst, $src2}", []>, XS;
-def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
- "mulsd {$src2, $dst|$dst, $src2}", []>, XD;
-
-def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
- "divss {$src2, $dst|$dst, $src2}", []>, XS;
-def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "divss {$src2, $dst|$dst, $src2}",
- [(set V4F4:$dst, (fdiv V4F4:$src1, V4F4:$src2))]>, XS;
-def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
- "divsd {$src2, $dst|$dst, $src2}", []>, XD;
-def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "divsd {$src2, $dst|$dst, $src2}",
- [(set V2F8:$dst, (fdiv V2F8:$src1, V2F8:$src2))]>, XD;
-
-def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
- "subss {$src2, $dst|$dst, $src2}", []>, XS;
-def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "subss {$src2, $dst|$dst, $src2}",
- [(set V4F4:$dst, (fsub V4F4:$src1, V4F4:$src2))]>, XS;
-def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
- "subsd {$src2, $dst|$dst, $src2}", []>, XD;
-def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "subsd {$src2, $dst|$dst, $src2}",
- [(set V2F8:$dst, (fsub V2F8:$src1, V2F8:$src2))]>, XD;
-
-def CMPSSrr : I<0xC2, MRMSrcReg,
- (ops V4F4:$dst, V4F4:$src1, V4F4:$src, SSECC:$cc),
- "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS;
-def CMPSSrm : I<0xC2, MRMSrcMem,
- (ops V4F4:$dst, V4F4:$src1, f32mem:$src, SSECC:$cc),
- "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS;
-def CMPSDrr : I<0xC2, MRMSrcReg,
- (ops V2F8:$dst, V2F8:$src1, V2F8:$src, SSECC:$cc),
- "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD;
-def CMPSDrm : I<0xC2, MRMSrcMem,
- (ops V2F8:$dst, V2F8:$src1, f64mem:$src, SSECC:$cc),
- "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD;
-}
+// (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
+def : Pat<(or (srl R32:$src1, CL:$amt),
+ (shl R32:$src2, (sub 32, CL:$amt))),
+ (SHRD32rrCL R32:$src1, R32:$src2)>;
-//===----------------------------------------------------------------------===//
-// Miscellaneous Instructions
-//===----------------------------------------------------------------------===//
+def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
+ (shl R32:$src2, (sub 32, CL:$amt))), addr:$dst),
+ (SHRD32mrCL addr:$dst, R32:$src2)>;
-def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", []>, TB, Imp<[],[EAX,EDX]>;
+// (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
+def : Pat<(or (shl R32:$src1, CL:$amt),
+ (srl R32:$src2, (sub 32, CL:$amt))),
+ (SHLD32rrCL R32:$src1, R32:$src2)>;
+
+def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
+ (srl R32:$src2, (sub 32, CL:$amt))), addr:$dst),
+ (SHLD32mrCL addr:$dst, R32:$src2)>;
+
+// (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
+def : Pat<(or (srl R16:$src1, CL:$amt),
+ (shl R16:$src2, (sub 16, CL:$amt))),
+ (SHRD16rrCL R16:$src1, R16:$src2)>;
+
+def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
+ (shl R16:$src2, (sub 16, CL:$amt))), addr:$dst),
+ (SHRD16mrCL addr:$dst, R16:$src2)>;
+
+// (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
+def : Pat<(or (shl R16:$src1, CL:$amt),
+ (srl R16:$src2, (sub 16, CL:$amt))),
+ (SHLD16rrCL R16:$src1, R16:$src2)>;
+
+def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
+ (srl R16:$src2, (sub 16, CL:$amt))), addr:$dst),
+ (SHLD16mrCL addr:$dst, R16:$src2)>;
//===----------------------------------------------------------------------===//
-// Stack-based Floating point support
+// Floating Point Stack Support
//===----------------------------------------------------------------------===//
-// FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
+include "X86InstrFPStack.td"
-// Floating point instruction template
-class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm>
- : X86Inst<o, F, NoImm, ops, asm> {
- let FPForm = fp; let FPFormBits = FPForm.Value;
-}
+//===----------------------------------------------------------------------===//
+// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
+//===----------------------------------------------------------------------===//
-// Pseudo instructions for floating point. We use these pseudo instructions
-// because they can be expanded by the fp spackifier into one of many different
-// forms of instructions for doing these operations. Until the stackifier runs,
-// we prefer to be abstract.
-def FpMOV : FPI<0, Pseudo, SpecialFP,
- (ops RFP:$dst, RFP:$src), "">; // f1 = fmov f2
-def FpADD : FPI<0, Pseudo, TwoArgFP ,
- (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fadd f2, f3
-def FpSUB : FPI<0, Pseudo, TwoArgFP ,
- (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fsub f2, f3
-def FpMUL : FPI<0, Pseudo, TwoArgFP ,
- (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fmul f2, f3
-def FpDIV : FPI<0, Pseudo, TwoArgFP ,
- (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fdiv f2, f3
-
-def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$dst), "">,
- Imp<[ST0], []>; // FPR = ST(0)
-
-def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$src), "">,
- Imp<[], [ST0]>; // ST(0) = FPR
-
-// FADD reg, mem: Before stackification, these are represented by:
-// R1 = FADD* R2, [mem]
-def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real]
- (ops f32mem:$src, variable_ops),
- "fadd{s} $src">;
-def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real]
- (ops f64mem:$src, variable_ops),
- "fadd{l} $src">;
-//def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
-//def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
-
-// FMUL reg, mem: Before stackification, these are represented by:
-// R1 = FMUL* R2, [mem]
-def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real]
- (ops f32mem:$src, variable_ops),
- "fmul{s} $src">;
-def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real]
- (ops f64mem:$src, variable_ops),
- "fmul{l} $src">;
-// ST(0) = ST(0) * [mem16int]
-//def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>;
-// ST(0) = ST(0) * [mem32int]
-//def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>;
-
-// FSUB reg, mem: Before stackification, these are represented by:
-// R1 = FSUB* R2, [mem]
-def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real]
- (ops f32mem:$src, variable_ops),
- "fsub{s} $src">;
-def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real]
- (ops f64mem:$src, variable_ops),
- "fsub{l} $src">;
-// ST(0) = ST(0) - [mem16int]
-//def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>;
-// ST(0) = ST(0) - [mem32int]
-//def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>;
-
-// FSUBR reg, mem: Before stackification, these are represented by:
-// R1 = FSUBR* R2, [mem]
-
-// Note that the order of operands does not reflect the operation being
-// performed.
-def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0)
- (ops f32mem:$src, variable_ops),
- "fsubr{s} $src">;
-def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0)
- (ops f64mem:$src, variable_ops),
- "fsubr{l} $src">;
-// ST(0) = [mem16int] - ST(0)
-//def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>;
-// ST(0) = [mem32int] - ST(0)
-//def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>;
-
-// FDIV reg, mem: Before stackification, these are represented by:
-// R1 = FDIV* R2, [mem]
-def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real]
- (ops f32mem:$src, variable_ops),
- "fdiv{s} $src">;
-def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real]
- (ops f64mem:$src, variable_ops),
- "fdiv{l} $src">;
-// ST(0) = ST(0) / [mem16int]
-//def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>;
-// ST(0) = ST(0) / [mem32int]
-//def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>;
-
-// FDIVR reg, mem: Before stackification, these are represented by:
-// R1 = FDIVR* R2, [mem]
-// Note that the order of operands does not reflect the operation being
-// performed.
-def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0)
- (ops f32mem:$src, variable_ops),
- "fdivr{s} $src">;
-def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0)
- (ops f64mem:$src, variable_ops),
- "fdivr{l} $src">;
-// ST(0) = [mem16int] / ST(0)
-//def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>;
-// ST(0) = [mem32int] / ST(0)
-//def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>;
-
-
-// Floating point cmovs...
-let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
- def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
- def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
- def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
- def FCMOVP : FPI<0xD8, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA;
- def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
- def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
- def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
- def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB;
-}
+include "X86InstrMMX.td"
-// Floating point loads & stores...
-// FIXME: these are all marked variable_ops because they have an implicit
-// destination. Instructions like FILD* that are generated by the instruction
-// selector (not the fp stackifier) need more accurate operand accounting.
-def FLDrr : FPI<0xC0, AddRegFrm, NotFP,
- (ops RST:$src, variable_ops),
- "fld $src">, D9;
-def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP,
- (ops f32mem:$src, variable_ops),
- "fld{s} $src">;
-def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP,
- (ops f64mem:$src, variable_ops),
- "fld{l} $src">;
-def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP,
- (ops f80mem:$src, variable_ops),
- "fld{t} $src">;
-def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP,
- (ops i16mem:$src, variable_ops),
- "fild{s} $src">;
-def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP,
- (ops i32mem:$src, variable_ops),
- "fild{l} $src">;
-def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP,
- (ops i64mem:$src, variable_ops),
- "fild{ll} $src">;
-
-def FSTrr : FPI<0xD0, AddRegFrm, NotFP,
- (ops RST:$op, variable_ops),
- "fst $op">, DD;
-def FSTPrr : FPI<0xD8, AddRegFrm, NotFP,
- (ops RST:$op, variable_ops),
- "fstp $op">, DD;
-def FST32m : FPI<0xD9, MRM2m, OneArgFP,
- (ops f32mem:$op, variable_ops),
- "fst{s} $op">;
-def FST64m : FPI<0xDD, MRM2m, OneArgFP,
- (ops f64mem:$op, variable_ops),
- "fst{l} $op">;
-def FSTP32m : FPI<0xD9, MRM3m, OneArgFP,
- (ops f32mem:$op, variable_ops),
- "fstp{s} $op">;
-def FSTP64m : FPI<0xDD, MRM3m, OneArgFP,
- (ops f64mem:$op, variable_ops),
- "fstp{l} $op">;
-def FSTP80m : FPI<0xDB, MRM7m, OneArgFP,
- (ops f80mem:$op, variable_ops),
- "fstp{t} $op">;
-
-def FIST16m : FPI<0xDF, MRM2m , OneArgFP,
- (ops i16mem:$op, variable_ops),
- "fist{s} $op">;
-def FIST32m : FPI<0xDB, MRM2m , OneArgFP,
- (ops i32mem:$op, variable_ops),
- "fist{l} $op">;
-def FISTP16m : FPI<0xDF, MRM3m , NotFP ,
- (ops i16mem:$op, variable_ops),
- "fistp{s} $op">;
-def FISTP32m : FPI<0xDB, MRM3m , NotFP ,
- (ops i32mem:$op, variable_ops),
- "fistp{l} $op">;
-def FISTP64m : FPI<0xDF, MRM7m , OneArgFP,
- (ops i64mem:$op, variable_ops),
- "fistp{ll} $op">;
-
-def FXCH : FPI<0xC8, AddRegFrm, NotFP,
- (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
-
-// Floating point constant loads...
-def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops variable_ops), "fldz">, D9;
-def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops variable_ops), "fld1">, D9;
-
-
-// Unary operations...
-def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, // f1 = fchs f2
- (ops variable_ops),
- "fchs">, D9;
-def FABS : FPI<0xE1, RawFrm, OneArgFPRW, // f1 = fabs f2
- (ops variable_ops),
- "fabs">, D9;
-def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW, // fsqrt ST(0)
- (ops variable_ops),
- "fsqrt">, D9;
-def FSIN : FPI<0xFE, RawFrm, OneArgFPRW, // fsin ST(0)
- (ops variable_ops),
- "fsin">, D9;
-def FCOS : FPI<0xFF, RawFrm, OneArgFPRW, // fcos ST(0)
- (ops variable_ops),
- "fcos">, D9;
-def FTST : FPI<0xE4, RawFrm, OneArgFP , // ftst ST(0)
- (ops variable_ops),
- "ftst">, D9;
-
-// Binary arithmetic operations...
-class FPST0rInst<bits<8> o, dag ops, string asm>
- : I<o, AddRegFrm, ops, asm, []>, D8 {
- list<Register> Uses = [ST0];
- list<Register> Defs = [ST0];
-}
-class FPrST0Inst<bits<8> o, dag ops, string asm>
- : I<o, AddRegFrm, ops, asm, []>, DC {
- list<Register> Uses = [ST0];
-}
-class FPrST0PInst<bits<8> o, dag ops, string asm>
- : I<o, AddRegFrm, ops, asm, []>, DE {
- list<Register> Uses = [ST0];
-}
+//===----------------------------------------------------------------------===//
+// XMM Floating point support (requires SSE / SSE2)
+//===----------------------------------------------------------------------===//
-def FADDST0r : FPST0rInst <0xC0, (ops RST:$op),
- "fadd $op">;
-def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op),
- "fadd {%ST(0), $op|$op, %ST(0)}">;
-def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op),
- "faddp $op">;
-
-// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
-// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
-// we have to put some 'r's in and take them out of weird places.
-def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op),
- "fsubr $op">;
-def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op),
- "fsub{r} {%ST(0), $op|$op, %ST(0)}">;
-def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op),
- "fsub{r}p $op">;
-
-def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op),
- "fsub $op">;
-def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op),
- "fsub{|r} {%ST(0), $op|$op, %ST(0)}">;
-def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op),
- "fsub{|r}p $op">;
-
-def FMULST0r : FPST0rInst <0xC8, (ops RST:$op),
- "fmul $op">;
-def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op),
- "fmul {%ST(0), $op|$op, %ST(0)}">;
-def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op),
- "fmulp $op">;
-
-def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op),
- "fdivr $op">;
-def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op),
- "fdiv{r} {%ST(0), $op|$op, %ST(0)}">;
-def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op),
- "fdiv{r}p $op">;
-
-def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i)
- "fdiv $op">;
-def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i)
- "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">;
-def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop
- "fdiv{|r}p $op">;
-
-// Floating point compares
-def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i)
- (ops RST:$reg, variable_ops),
- "fucom $reg">, DD, Imp<[ST0],[]>;
-def FUCOMPr : I<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
- (ops RST:$reg, variable_ops),
- "fucomp $reg", []>, DD, Imp<[ST0],[]>;
-def FUCOMPPr : I<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
- (ops variable_ops),
- "fucompp", []>, DA, Imp<[ST0],[]>;
-
-def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i)
- (ops RST:$reg, variable_ops),
- "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
-def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
- (ops RST:$reg, variable_ops),
- "fucomip {$reg, %ST(0)|%ST(0), $reg}", []>, DF, Imp<[ST0],[]>;
-
-
-// Floating point flag ops
-def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
- (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
-
-def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
- (ops i16mem:$dst), "fnstcw $dst", []>;
-def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
- (ops i16mem:$dst), "fldcw $dst", []>;
+include "X86InstrSSE.td"
projects / oota-llvm.git / blobdiff