-//===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
+//===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
+// X86 specific DAG Nodes.
+//
+
+def SDTIntShiftDOp: SDTypeProfile<1, 3,
+ [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
+ SDTCisInt<0>, SDTCisInt<3>]>;
+
+def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
+
+def SDTX86Cmov : SDTypeProfile<1, 4,
+ [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
+ SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
+
+def SDTX86BrCond : SDTypeProfile<0, 3,
+ [SDTCisVT<0, OtherVT>,
+ SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
+
+def SDTX86SetCC : SDTypeProfile<1, 2,
+ [SDTCisVT<0, i8>,
+ SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
+
+def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
+
+def SDT_X86CallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
+def SDT_X86CallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
+ SDTCisVT<1, i32> ]>;
+
+def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
+
+def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
+
+def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
+
+def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
+
+def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
+
+def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
+
+def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
+
+def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
+
+def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
+def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
+def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
+def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
+
+def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
+
+def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
+def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
+ [SDNPHasChain]>;
+def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
+
+def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
+ [SDNPHasChain, SDNPOptInFlag]>;
+
+def X86callseq_start :
+ SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
+ [SDNPHasChain, SDNPOutFlag]>;
+def X86callseq_end :
+ SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+
+def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
+ [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
+
+def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
+ [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
+
+def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
+ [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
+ [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+
+def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
+ [SDNPHasChain, SDNPOutFlag]>;
+
+def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
+def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
+
+def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
+ [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
+def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
+
+def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
+ [SDNPHasChain]>;
+
+def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
+ [SDNPHasChain, SDNPOptInFlag]>;
+
+//===----------------------------------------------------------------------===//
+// X86 Operand Definitions.
+//
+
// *mem - Operand definitions for the funky X86 addressing mode operands.
//
-class X86MemOperand<ValueType Ty, string printMethod> : Operand<Ty> {
+class X86MemOperand<string printMethod> : Operand<iPTR> {
let PrintMethod = printMethod;
- let NumMIOperands = 4;
- let MIOperandInfo = (ops R32, i8imm, R32, i32imm);
+ let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
}
-def i8mem : X86MemOperand<i32, "printi8mem">;
-def i16mem : X86MemOperand<i32, "printi16mem">;
-def i32mem : X86MemOperand<i32, "printi32mem">;
-def i64mem : X86MemOperand<i32, "printi64mem">;
-def f32mem : X86MemOperand<i32, "printf32mem">;
-def f64mem : X86MemOperand<i32, "printf64mem">;
-def f80mem : X86MemOperand<i32, "printf80mem">;
+def i8mem : X86MemOperand<"printi8mem">;
+def i16mem : X86MemOperand<"printi16mem">;
+def i32mem : X86MemOperand<"printi32mem">;
+def i64mem : X86MemOperand<"printi64mem">;
+def i128mem : X86MemOperand<"printi128mem">;
+def f32mem : X86MemOperand<"printf32mem">;
+def f64mem : X86MemOperand<"printf64mem">;
+def f80mem : X86MemOperand<"printf80mem">;
+def f128mem : X86MemOperand<"printf128mem">;
+
+def lea32mem : Operand<i32> {
+ let PrintMethod = "printi32mem";
+ let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
+}
def SSECC : Operand<i8> {
let PrintMethod = "printSSECC";
}
+def piclabel: Operand<i32> {
+ let PrintMethod = "printPICLabel";
+}
+
// A couple of more descriptive operand definitions.
// 16-bits but only 8 bits are significant.
def i16i8imm : Operand<i16>;
// 32-bits but only 8 bits are significant.
def i32i8imm : Operand<i32>;
-// PCRelative calls need special operand formatting.
-let PrintMethod = "printCallOperand" in
- def calltarget : Operand<i32>;
-
// Branch targets have OtherVT type.
def brtarget : Operand<OtherVT>;
-// Define X86 specific addressing mode.
-def addr : ComplexPattern<i32, 4, "SelectAddr", []>;
-def leaaddr : ComplexPattern<i32, 4, "SelectLEAAddr",
- [add,
- frameindex, constpool, globaladdr, externalsym]>;
-
-// Format specifies the encoding used by the instruction. This is part of the
-// ad-hoc solution used to emit machine instruction encodings by our machine
-// code emitter.
-class Format<bits<5> val> {
- bits<5> Value = val;
-}
-
-def Pseudo : Format<0>; def RawFrm : Format<1>;
-def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
-def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
-def MRMSrcMem : Format<6>;
-def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
-def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
-def MRM6r : Format<22>; def MRM7r : Format<23>;
-def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
-def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
-def MRM6m : Format<30>; def MRM7m : Format<31>;
-
-// ImmType - This specifies the immediate type used by an instruction. This is
-// part of the ad-hoc solution used to emit machine instruction encodings by our
-// machine code emitter.
-class ImmType<bits<2> val> {
- bits<2> Value = val;
-}
-def NoImm : ImmType<0>;
-def Imm8 : ImmType<1>;
-def Imm16 : ImmType<2>;
-def Imm32 : ImmType<3>;
-
-// FPFormat - This specifies what form this FP instruction has. This is used by
-// the Floating-Point stackifier pass.
-class FPFormat<bits<3> val> {
- bits<3> Value = val;
-}
-def NotFP : FPFormat<0>;
-def ZeroArgFP : FPFormat<1>;
-def OneArgFP : FPFormat<2>;
-def OneArgFPRW : FPFormat<3>;
-def TwoArgFP : FPFormat<4>;
-def CompareFP : FPFormat<5>;
-def CondMovFP : FPFormat<6>;
-def SpecialFP : FPFormat<7>;
-
-
-class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
- : Instruction {
- let Namespace = "X86";
-
- bits<8> Opcode = opcod;
- Format Form = f;
- bits<5> FormBits = Form.Value;
- ImmType ImmT = i;
- bits<2> ImmTypeBits = ImmT.Value;
-
- dag OperandList = ops;
- string AsmString = AsmStr;
-
- //
- // Attributes specific to X86 instructions...
- //
- bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
-
- bits<4> Prefix = 0; // Which prefix byte does this inst have?
- FPFormat FPForm; // What flavor of FP instruction is this?
- bits<3> FPFormBits = 0;
-}
+//===----------------------------------------------------------------------===//
+// X86 Complex Pattern Definitions.
+//
-class Imp<list<Register> uses, list<Register> defs> {
- list<Register> Uses = uses;
- list<Register> Defs = defs;
-}
+// Define X86 specific addressing mode.
+def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
+def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
+ [add, mul, shl, or, frameindex], []>;
+//===----------------------------------------------------------------------===//
+// X86 Instruction Predicate Definitions.
+def HasMMX : Predicate<"Subtarget->hasMMX()">;
+def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
+def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
+def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
+def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
+def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
+def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
+def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
+def In64BitMode : Predicate<"Subtarget->is64Bit()">;
+def HasLow4G : Predicate<"Subtarget->hasLow4GUserSpaceAddress()">;
+def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
+def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
+def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
-// Prefix byte classes which are used to indicate to the ad-hoc machine code
-// emitter that various prefix bytes are required.
-class OpSize { bit hasOpSizePrefix = 1; }
-class TB { bits<4> Prefix = 1; }
-class REP { bits<4> Prefix = 2; }
-class D8 { bits<4> Prefix = 3; }
-class D9 { bits<4> Prefix = 4; }
-class DA { bits<4> Prefix = 5; }
-class DB { bits<4> Prefix = 6; }
-class DC { bits<4> Prefix = 7; }
-class DD { bits<4> Prefix = 8; }
-class DE { bits<4> Prefix = 9; }
-class DF { bits<4> Prefix = 10; }
-class XD { bits<4> Prefix = 11; }
-class XS { bits<4> Prefix = 12; }
+//===----------------------------------------------------------------------===//
+// X86 Instruction Format Definitions.
+//
+include "X86InstrFormats.td"
//===----------------------------------------------------------------------===//
// Pattern fragments...
//
+
+// X86 specific condition code. These correspond to CondCode in
+// X86InstrInfo.h. They must be kept in synch.
+def X86_COND_A : PatLeaf<(i8 0)>;
+def X86_COND_AE : PatLeaf<(i8 1)>;
+def X86_COND_B : PatLeaf<(i8 2)>;
+def X86_COND_BE : PatLeaf<(i8 3)>;
+def X86_COND_E : PatLeaf<(i8 4)>;
+def X86_COND_G : PatLeaf<(i8 5)>;
+def X86_COND_GE : PatLeaf<(i8 6)>;
+def X86_COND_L : PatLeaf<(i8 7)>;
+def X86_COND_LE : PatLeaf<(i8 8)>;
+def X86_COND_NE : PatLeaf<(i8 9)>;
+def X86_COND_NO : PatLeaf<(i8 10)>;
+def X86_COND_NP : PatLeaf<(i8 11)>;
+def X86_COND_NS : PatLeaf<(i8 12)>;
+def X86_COND_O : PatLeaf<(i8 13)>;
+def X86_COND_P : PatLeaf<(i8 14)>;
+def X86_COND_S : PatLeaf<(i8 15)>;
+
def i16immSExt8 : PatLeaf<(i16 imm), [{
// i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
// sign extended field.
- return (int)N->getValue() == (signed char)N->getValue();
+ return (int16_t)N->getValue() == (int8_t)N->getValue();
}]>;
def i32immSExt8 : PatLeaf<(i32 imm), [{
// i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
// sign extended field.
- return (int)N->getValue() == (signed char)N->getValue();
-}]>;
-
-def i16immZExt8 : PatLeaf<(i16 imm), [{
- // i16immZExt8 predicate - True if the 16-bit immediate fits in a 8-bit zero
- // extended field.
- return (unsigned)N->getValue() == (unsigned char)N->getValue();
+ return (int32_t)N->getValue() == (int8_t)N->getValue();
}]>;
// Helper fragments for loads.
def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
-
-def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i1))>;
-def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i1))>;
-def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextload node:$ptr, i8))>;
-def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i8))>;
-def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextload node:$ptr, i16))>;
-
-def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i1))>;
-def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i1))>;
-def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextload node:$ptr, i8))>;
-def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i8))>;
-def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextload node:$ptr, i16))>;
-
+def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
+
+def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
+def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
+def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
+
+def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
+def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
+def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
+def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
+def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
+
+def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
+def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
+def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
+def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
+def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
+def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
+
+def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
+def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
+def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
+def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
+def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
+def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
//===----------------------------------------------------------------------===//
-// Instruction templates...
+// Instruction list...
+//
-class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
- : X86Inst<o, f, NoImm, ops, asm> {
- let Pattern = pattern;
-}
-class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
- : X86Inst<o, f, Imm8 , ops, asm> {
- let Pattern = pattern;
-}
-class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
- : X86Inst<o, f, Imm16, ops, asm> {
- let Pattern = pattern;
+// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
+// a stack adjustment and the codegen must know that they may modify the stack
+// pointer before prolog-epilog rewriting occurs.
+// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become sub / add
+// which can clobber EFLAGS.
+let Defs = [ESP, EFLAGS], Uses = [ESP] in {
+def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt),
+ "#ADJCALLSTACKDOWN",
+ [(X86callseq_start imm:$amt)]>;
+def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
+ "#ADJCALLSTACKUP",
+ [(X86callseq_end imm:$amt1, imm:$amt2)]>;
}
-class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
- : X86Inst<o, f, Imm32, ops, asm> {
- let Pattern = pattern;
+def IMPLICIT_USE : I<0, Pseudo, (outs), (ins variable_ops),
+ "#IMPLICIT_USE", []>;
+let isImplicitDef = 1 in {
+def IMPLICIT_DEF : I<0, Pseudo, (outs variable_ops), (ins),
+ "#IMPLICIT_DEF", []>;
+def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
+ "#IMPLICIT_DEF $dst",
+ [(set GR8:$dst, (undef))]>;
+def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
+ "#IMPLICIT_DEF $dst",
+ [(set GR16:$dst, (undef))]>;
+def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
+ "#IMPLICIT_DEF $dst",
+ [(set GR32:$dst, (undef))]>;
}
-//===----------------------------------------------------------------------===//
-// Instruction list...
-//
-
-def PHI : I<0, Pseudo, (ops variable_ops), "PHINODE", []>; // PHI node.
-def NOOP : I<0x90, RawFrm, (ops), "nop", []>; // nop
+// Nop
+def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
-def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN", []>;
-def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
- "#ADJCALLSTACKUP", []>;
-def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
-def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
-let isTerminator = 1 in
- let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
- def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
//===----------------------------------------------------------------------===//
// Control Flow Instructions...
//
// Return instructions.
-let isTerminator = 1, isReturn = 1, isBarrier = 1 in
- def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
-let isTerminator = 1, isReturn = 1, isBarrier = 1 in
- def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
+let isTerminator = 1, isReturn = 1, isBarrier = 1,
+ hasCtrlDep = 1 in {
+ def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
+ def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
+ [(X86retflag imm:$amt)]>;
+}
// All branches are RawFrm, Void, Branch, and Terminators
let isBranch = 1, isTerminator = 1 in
- class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
- I<opcode, RawFrm, ops, asm, pattern>;
-
-let isBarrier = 1 in
- def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
-def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
- []>, TB;
-def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst", []>, TB;
-def JE : IBr<0x84, (ops brtarget:$dst), "je $dst", []>, TB;
-def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst", []>, TB;
-def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst", []>, TB;
-def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst", []>, TB;
-def JS : IBr<0x88, (ops brtarget:$dst), "js $dst", []>, TB;
-def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst", []>, TB;
-def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst", []>, TB;
-def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst", []>, TB;
-def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst", []>, TB;
-def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst", []>, TB;
-def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst", []>, TB;
-def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst", []>, TB;
+ class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
+ I<opcode, RawFrm, (outs), ins, asm, pattern>;
+
+let isBranch = 1, isBarrier = 1 in
+ def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
+
+// Indirect branches
+let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
+ def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
+ [(brind GR32:$dst)]>;
+ def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
+ [(brind (loadi32 addr:$dst))]>;
+}
+
+// Conditional branches
+let Uses = [EFLAGS] in {
+def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
+ [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
+def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
+ [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
+def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
+ [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
+def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
+ [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
+def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
+ [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
+def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
+ [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
+
+def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
+ [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
+def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
+ [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
+def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
+ [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
+def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
+ [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
+
+def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
+ [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
+def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
+ [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
+def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
+ [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
+def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
+ [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
+def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
+ [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
+def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
+ [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
+} // Uses = [EFLAGS]
//===----------------------------------------------------------------------===//
// Call Instructions...
let isCall = 1 in
// All calls clobber the non-callee saved registers...
let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
- XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
- def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst", []>;
- def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst", []>;
- def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst", []>;
+ MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
+ XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, EFLAGS] in {
+ def CALLpcrel32 : I<0xE8, RawFrm, (outs), (ins i32imm:$dst, variable_ops),
+ "call\t${dst:call}", []>;
+ def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
+ "call\t{*}$dst", [(X86call GR32:$dst)]>;
+ def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
+ "call\t{*}$dst", []>;
}
// Tail call stuff.
+
+def TAILCALL : I<0, Pseudo, (outs), (ins ),
+ "#TAILCALL",
+ []>;
+
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
- def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL", []>;
+def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset),
+ "#TC_RETURN $dst $offset",
+ []>;
+
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
- def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL", []>;
+def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset),
+ "#TC_RETURN $dst $offset",
+ []>;
+
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
- def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
- "jmp {*}$dst # TAIL CALL", []>;
-
-// ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every
-// way, except that it is marked as being a terminator. This causes the epilog
-// inserter to insert reloads of callee saved registers BEFORE this. We need
-// this until we have a more accurate way of tracking where the stack pointer is
-// within a function.
-let isTerminator = 1, isTwoAddress = 1 in
- def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
- "add{l} {$src2, $dst|$dst, $src2}", []>;
+ def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAILCALL",
+ []>;
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
+ def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
+ []>;
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
+ def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
+ "jmp\t{*}$dst # TAILCALL", []>;
//===----------------------------------------------------------------------===//
// Miscellaneous Instructions...
//
+let Defs = [EBP, ESP], Uses = [EBP, ESP] in
def LEAVE : I<0xC9, RawFrm,
- (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
-def POP32r : I<0x58, AddRegFrm,
- (ops R32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
+ (outs), (ins), "leave", []>;
+
+let Defs = [ESP], Uses = [ESP] in {
+def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
-let isTwoAddress = 1 in // R32 = bswap R32
+def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
+}
+
+let Defs = [ESP, EFLAGS], Uses = [ESP] in
+def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
+let Defs = [ESP], Uses = [ESP, EFLAGS] in
+def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
+
+def MovePCtoStack : I<0, Pseudo, (outs), (ins piclabel:$label),
+ "call\t$label", []>;
+
+let isTwoAddress = 1 in // GR32 = bswap GR32
def BSWAP32r : I<0xC8, AddRegFrm,
- (ops R32:$dst, R32:$src), "bswap{l} $dst", []>, TB;
-
-def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
- (ops R8:$src1, R8:$src2),
- "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
-def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
- (ops R16:$src1, R16:$src2),
- "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
-def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
- (ops R32:$src1, R32:$src2),
- "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
+ (outs GR32:$dst), (ins GR32:$src),
+ "bswap{l}\t$dst",
+ [(set GR32:$dst, (bswap GR32:$src))]>, TB;
+
+// FIXME: Model xchg* as two address instructions?
+def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
+ (outs), (ins GR8:$src1, GR8:$src2),
+ "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
+def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
+ (outs), (ins GR16:$src1, GR16:$src2),
+ "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
+def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
+ (outs), (ins GR32:$src1, GR32:$src2),
+ "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG8mr : I<0x86, MRMDestMem,
- (ops i8mem:$src1, R8:$src2),
- "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
+ (outs), (ins i8mem:$src1, GR8:$src2),
+ "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG16mr : I<0x87, MRMDestMem,
- (ops i16mem:$src1, R16:$src2),
- "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
+ (outs), (ins i16mem:$src1, GR16:$src2),
+ "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
def XCHG32mr : I<0x87, MRMDestMem,
- (ops i32mem:$src1, R32:$src2),
- "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
+ (outs), (ins i32mem:$src1, GR32:$src2),
+ "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG8rm : I<0x86, MRMSrcMem,
- (ops R8:$src1, i8mem:$src2),
- "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
+ (outs), (ins GR8:$src1, i8mem:$src2),
+ "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
def XCHG16rm : I<0x87, MRMSrcMem,
- (ops R16:$src1, i16mem:$src2),
- "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
+ (outs), (ins GR16:$src1, i16mem:$src2),
+ "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
def XCHG32rm : I<0x87, MRMSrcMem,
- (ops R32:$src1, i32mem:$src2),
- "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
+ (outs), (ins GR32:$src1, i32mem:$src2),
+ "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
+
+// Bit scan instructions.
+let Defs = [EFLAGS] in {
+def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
+ "bsf{w}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
+def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+ "bsf{w}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
+ (implicit EFLAGS)]>, TB;
+def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
+ "bsf{l}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
+def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
+ "bsf{l}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
+ (implicit EFLAGS)]>, TB;
+
+def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
+ "bsr{w}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
+def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+ "bsr{w}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
+ (implicit EFLAGS)]>, TB;
+def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
+ "bsr{l}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
+def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
+ "bsr{l}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
+ (implicit EFLAGS)]>, TB;
+} // Defs = [EFLAGS]
def LEA16r : I<0x8D, MRMSrcMem,
- (ops R16:$dst, i32mem:$src),
- "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
+ (outs GR16:$dst), (ins i32mem:$src),
+ "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
def LEA32r : I<0x8D, MRMSrcMem,
- (ops R32:$dst, i32mem:$src),
- "lea{l} {$src|$dst}, {$dst|$src}",
- [(set R32:$dst, leaaddr:$src)]>;
-
-def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}", []>,
- Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
-def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}", []>,
- Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
-def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}", []>,
- Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
+ (outs GR32:$dst), (ins lea32mem:$src),
+ "lea{l}\t{$src|$dst}, {$dst|$src}",
+ [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
+
+let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
+def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
+ [(X86rep_movs i8)]>, REP;
+def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
+ [(X86rep_movs i16)]>, REP, OpSize;
+def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
+ [(X86rep_movs i32)]>, REP;
+}
-def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}", []>,
- Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
-def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}", []>,
- Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
-def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>,
- Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
+let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
+def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
+ [(X86rep_stos i8)]>, REP;
+let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
+def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
+ [(X86rep_stos i16)]>, REP, OpSize;
+let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
+def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
+ [(X86rep_stos i32)]>, REP;
+let Defs = [RAX, RDX] in
+def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
+ TB;
//===----------------------------------------------------------------------===//
// Input/Output Instructions...
//
-def IN8rr : I<0xEC, RawFrm, (ops),
- "in{b} {%dx, %al|%AL, %DX}", []>, Imp<[DX], [AL]>;
-def IN16rr : I<0xED, RawFrm, (ops),
- "in{w} {%dx, %ax|%AX, %DX}", []>, Imp<[DX], [AX]>, OpSize;
-def IN32rr : I<0xED, RawFrm, (ops),
- "in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>;
-
-def IN8ri : Ii8<0xE4, RawFrm, (ops i8imm:$port),
- "in{b} {$port, %al|%AL, $port}", []>, Imp<[], [AL]>;
-def IN16ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
- "in{w} {$port, %ax|%AX, $port}", []>, Imp<[], [AX]>, OpSize;
-def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
- "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
-
-def OUT8rr : I<0xEE, RawFrm, (ops),
- "out{b} {%al, %dx|%DX, %AL}",
- [(writeport AL, DX)]>, Imp<[DX, AL], []>;
-def OUT16rr : I<0xEF, RawFrm, (ops),
- "out{w} {%ax, %dx|%DX, %AX}",
- [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize;
-def OUT32rr : I<0xEF, RawFrm, (ops),
- "out{l} {%eax, %dx|%DX, %EAX}",
- [(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
-
-def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
- "out{b} {%al, $port|$port, %AL}",
- [(writeport AL, i16immZExt8:$port)]>,
- Imp<[AL], []>;
-def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
- "out{w} {%ax, $port|$port, %AX}",
- [(writeport AX, i16immZExt8:$port)]>,
- Imp<[AX], []>, OpSize;
-def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
- "out{l} {%eax, $port|$port, %EAX}",
- [(writeport EAX, i16immZExt8:$port)]>,
- Imp<[EAX], []>;
+let Defs = [AL], Uses = [DX] in
+def IN8rr : I<0xEC, RawFrm, (outs), (ins),
+ "in{b}\t{%dx, %al|%AL, %DX}", []>;
+let Defs = [AX], Uses = [DX] in
+def IN16rr : I<0xED, RawFrm, (outs), (ins),
+ "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
+let Defs = [EAX], Uses = [DX] in
+def IN32rr : I<0xED, RawFrm, (outs), (ins),
+ "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
+
+let Defs = [AL] in
+def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
+ "in{b}\t{$port, %al|%AL, $port}", []>;
+let Defs = [AX] in
+def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
+ "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
+let Defs = [EAX] in
+def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
+ "in{l}\t{$port, %eax|%EAX, $port}", []>;
+
+let Uses = [DX, AL] in
+def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
+ "out{b}\t{%al, %dx|%DX, %AL}", []>;
+let Uses = [DX, AX] in
+def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
+ "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
+let Uses = [DX, EAX] in
+def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
+ "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
+
+let Uses = [AL] in
+def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
+ "out{b}\t{%al, $port|$port, %AL}", []>;
+let Uses = [AX] in
+def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
+ "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
+let Uses = [EAX] in
+def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
+ "out{l}\t{%eax, $port|$port, %EAX}", []>;
//===----------------------------------------------------------------------===//
// Move Instructions...
//
-def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src),
- "mov{b} {$src, $dst|$dst, $src}", []>;
-def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src),
- "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
-def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src),
- "mov{l} {$src, $dst|$dst, $src}", []>;
-def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src),
- "mov{b} {$src, $dst|$dst, $src}",
- [(set R8:$dst, imm:$src)]>;
-def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src),
- "mov{w} {$src, $dst|$dst, $src}",
- [(set R16:$dst, imm:$src)]>, OpSize;
-def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src),
- "mov{l} {$src, $dst|$dst, $src}",
- [(set R32:$dst, imm:$src)]>;
-def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
- "mov{b} {$src, $dst|$dst, $src}",
+def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
+ "mov{b}\t{$src, $dst|$dst, $src}", []>;
+def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
+def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}", []>;
+let isReMaterializable = 1, neverHasSideEffects = 1 in {
+def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
+ "mov{b}\t{$src, $dst|$dst, $src}",
+ [(set GR8:$dst, imm:$src)]>;
+def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, imm:$src)]>, OpSize;
+def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, imm:$src)]>;
+}
+def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
+ "mov{b}\t{$src, $dst|$dst, $src}",
[(store (i8 imm:$src), addr:$dst)]>;
-def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
- "mov{w} {$src, $dst|$dst, $src}",
+def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}",
[(store (i16 imm:$src), addr:$dst)]>, OpSize;
-def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
- "mov{l} {$src, $dst|$dst, $src}",
+def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}",
[(store (i32 imm:$src), addr:$dst)]>;
-def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src),
- "mov{b} {$src, $dst|$dst, $src}",
- [(set R8:$dst, (load addr:$src))]>;
-def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src),
- "mov{w} {$src, $dst|$dst, $src}",
- [(set R16:$dst, (load addr:$src))]>, OpSize;
-def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src),
- "mov{l} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (load addr:$src))]>;
-
-def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src),
- "mov{b} {$src, $dst|$dst, $src}",
- [(store R8:$src, addr:$dst)]>;
-def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src),
- "mov{w} {$src, $dst|$dst, $src}",
- [(store R16:$src, addr:$dst)]>, OpSize;
-def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src),
- "mov{l} {$src, $dst|$dst, $src}",
- [(store R32:$src, addr:$dst)]>;
-
-// Handling 1 bit load
-def : Pat<(i1 (load addr:$src)), (MOV8rm addr:$src)>;
+let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
+def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
+ "mov{b}\t{$src, $dst|$dst, $src}",
+ [(set GR8:$dst, (load addr:$src))]>;
+def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (load addr:$src))]>, OpSize;
+def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (load addr:$src))]>;
+}
+def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
+ "mov{b}\t{$src, $dst|$dst, $src}",
+ [(store GR8:$src, addr:$dst)]>;
+def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}",
+ [(store GR16:$src, addr:$dst)]>, OpSize;
+def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}",
+ [(store GR32:$src, addr:$dst)]>;
+
//===----------------------------------------------------------------------===//
// Fixed-Register Multiplication and Division Instructions...
//
// Extra precision multiplication
-def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src", []>,
- Imp<[AL],[AX]>; // AL,AH = AL*R8
-def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src", []>,
- Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
-def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src", []>,
- Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
-def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
- "mul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
-def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
- "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
- OpSize; // AX,DX = AX*[mem16]
-def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
- "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
-
-def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src", []>,
- Imp<[AL],[AX]>; // AL,AH = AL*R8
-def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src", []>,
- Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
-def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src", []>,
- Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
-def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
- "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
-def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
- "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
- OpSize; // AX,DX = AX*[mem16]
-def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
- "imul{l} $src", []>,
- Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
+let Defs = [AL,AH,EFLAGS], Uses = [AL] in
+def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
+ // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
+ // This probably ought to be moved to a def : Pat<> if the
+ // syntax can be accepted.
+ [(set AL, (mul AL, GR8:$src))]>; // AL,AH = AL*GR8
+let Defs = [AX,DX,EFLAGS], Uses = [AX] in
+def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
+ OpSize; // AX,DX = AX*GR16
+let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
+def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>;
+ // EAX,EDX = EAX*GR32
+let Defs = [AL,AH,EFLAGS], Uses = [AL] in
+def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
+ "mul{b}\t$src",
+ // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
+ // This probably ought to be moved to a def : Pat<> if the
+ // syntax can be accepted.
+ [(set AL, (mul AL, (loadi8 addr:$src)))]>; // AL,AH = AL*[mem8]
+let Defs = [AX,DX,EFLAGS], Uses = [AX] in
+def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
+ "mul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
+let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
+def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
+ "mul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
+
+let Defs = [AL,AH,EFLAGS], Uses = [AL] in
+def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
+ // AL,AH = AL*GR8
+let Defs = [AX,DX,EFLAGS], Uses = [AX] in
+def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
+ OpSize; // AX,DX = AX*GR16
+let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
+def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
+ // EAX,EDX = EAX*GR32
+let Defs = [AL,AH,EFLAGS], Uses = [AL] in
+def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
+ "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
+let Defs = [AX,DX,EFLAGS], Uses = [AX] in
+def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
+ "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
+let Defs = [EAX,EDX], Uses = [EAX] in
+def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
+ "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
// unsigned division/remainder
-def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH
- "div{b} $src", []>, Imp<[AX],[AX]>;
-def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX
- "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
-def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
- "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
-def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
- "div{b} $src", []>, Imp<[AX],[AX]>;
-def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
- "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
-def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
- "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
+let Defs = [AX,EFLAGS], Uses = [AL,AH] in
+def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
+ "div{b}\t$src", []>;
+let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
+def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
+ "div{w}\t$src", []>, OpSize;
+let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
+def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
+ "div{l}\t$src", []>;
+let Defs = [AX,EFLAGS], Uses = [AL,AH] in
+def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
+ "div{b}\t$src", []>;
+let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
+def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
+ "div{w}\t$src", []>, OpSize;
+let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
+def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
+ "div{l}\t$src", []>;
// Signed division/remainder.
-def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH
- "idiv{b} $src", []>, Imp<[AX],[AX]>;
-def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX
- "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
-def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX
- "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
-def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
- "idiv{b} $src", []>, Imp<[AX],[AX]>;
-def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
- "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
-def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
- "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
-
-// Sign-extenders for division.
-def CBW : I<0x98, RawFrm, (ops),
- "{cbtw|cbw}", []>, Imp<[AL],[AH]>; // AX = signext(AL)
-def CWD : I<0x99, RawFrm, (ops),
- "{cwtd|cwd}", []>, Imp<[AX],[DX]>; // DX:AX = signext(AX)
-def CDQ : I<0x99, RawFrm, (ops),
- "{cltd|cdq}", []>, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
-
+let Defs = [AX,EFLAGS], Uses = [AL,AH] in
+def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
+ "idiv{b}\t$src", []>;
+let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
+def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
+ "idiv{w}\t$src", []>, OpSize;
+let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
+def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
+ "idiv{l}\t$src", []>;
+let Defs = [AX,EFLAGS], Uses = [AL,AH] in
+def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
+ "idiv{b}\t$src", []>;
+let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
+def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
+ "idiv{w}\t$src", []>, OpSize;
+let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
+def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
+ "idiv{l}\t$src", []>;
+
//===----------------------------------------------------------------------===//
// Two address Instructions...
let isTwoAddress = 1 in {
// Conditional moves
-def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovb {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovb {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovb {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovae {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovae {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovae {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmove {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmove {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmove {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovne {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovne {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovne {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovbe {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovbe {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovbe {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmova {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmova {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmova {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovs {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovs {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovs {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovns {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovns {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovns {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovp {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovp {$src2, $dst|$dst, $src2}", []>, TB;
-
-
-def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovnp {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovnp {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovnp {$src2, $dst|$dst, $src2}", []>, TB;
-
-
-def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovl {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovl {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovl {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovge {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovge {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovge {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovle {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovle {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovle {$src2, $dst|$dst, $src2}", []>, TB;
-
-def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16
- (ops R16:$dst, R16:$src1, R16:$src2),
- "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16]
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "cmovg {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32
- (ops R32:$dst, R32:$src1, R32:$src2),
- "cmovg {$src2, $dst|$dst, $src2}", []>, TB;
-def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32]
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "cmovg {$src2, $dst|$dst, $src2}", []>, TB;
+let Uses = [EFLAGS] in {
+let isCommutable = 1 in {
+def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovb\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_B, EFLAGS))]>,
+ TB, OpSize;
+def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovb\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_B, EFLAGS))]>,
+ TB;
+
+def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovae\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_AE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovae\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_AE, EFLAGS))]>,
+ TB;
+def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmove\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_E, EFLAGS))]>,
+ TB, OpSize;
+def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmove\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_E, EFLAGS))]>,
+ TB;
+def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovne\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_NE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovne\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_NE, EFLAGS))]>,
+ TB;
+def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovbe\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_BE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovbe\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_BE, EFLAGS))]>,
+ TB;
+def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmova\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_A, EFLAGS))]>,
+ TB, OpSize;
+def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmova\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_A, EFLAGS))]>,
+ TB;
+def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovl\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_L, EFLAGS))]>,
+ TB, OpSize;
+def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovl\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_L, EFLAGS))]>,
+ TB;
+def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovge\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_GE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovge\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_GE, EFLAGS))]>,
+ TB;
+def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovle\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_LE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovle\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_LE, EFLAGS))]>,
+ TB;
+def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovg\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_G, EFLAGS))]>,
+ TB, OpSize;
+def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovg\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_G, EFLAGS))]>,
+ TB;
+def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovs\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_S, EFLAGS))]>,
+ TB, OpSize;
+def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovs\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_S, EFLAGS))]>,
+ TB;
+def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovns\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_NS, EFLAGS))]>,
+ TB, OpSize;
+def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovns\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_NS, EFLAGS))]>,
+ TB;
+def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovp\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_P, EFLAGS))]>,
+ TB, OpSize;
+def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovp\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_P, EFLAGS))]>,
+ TB;
+def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "cmovnp\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
+ X86_COND_NP, EFLAGS))]>,
+ TB, OpSize;
+def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "cmovnp\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
+ X86_COND_NP, EFLAGS))]>,
+ TB;
+} // isCommutable = 1
+
+def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovnp\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_NP, EFLAGS))]>,
+ TB;
+
+def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovb\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_B, EFLAGS))]>,
+ TB, OpSize;
+def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovb\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_B, EFLAGS))]>,
+ TB;
+def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovae\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_AE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovae\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_AE, EFLAGS))]>,
+ TB;
+def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmove\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_E, EFLAGS))]>,
+ TB, OpSize;
+def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmove\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_E, EFLAGS))]>,
+ TB;
+def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovne\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_NE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovne\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_NE, EFLAGS))]>,
+ TB;
+def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovbe\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_BE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovbe\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_BE, EFLAGS))]>,
+ TB;
+def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmova\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_A, EFLAGS))]>,
+ TB, OpSize;
+def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmova\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_A, EFLAGS))]>,
+ TB;
+def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovl\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_L, EFLAGS))]>,
+ TB, OpSize;
+def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovl\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_L, EFLAGS))]>,
+ TB;
+def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovge\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_GE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovge\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_GE, EFLAGS))]>,
+ TB;
+def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovle\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_LE, EFLAGS))]>,
+ TB, OpSize;
+def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovle\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_LE, EFLAGS))]>,
+ TB;
+def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovg\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_G, EFLAGS))]>,
+ TB, OpSize;
+def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovg\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_G, EFLAGS))]>,
+ TB;
+def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovs\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_S, EFLAGS))]>,
+ TB, OpSize;
+def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovs\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_S, EFLAGS))]>,
+ TB;
+def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovns\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_NS, EFLAGS))]>,
+ TB, OpSize;
+def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovns\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_NS, EFLAGS))]>,
+ TB;
+def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovp\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_P, EFLAGS))]>,
+ TB, OpSize;
+def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "cmovp\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
+ X86_COND_P, EFLAGS))]>,
+ TB;
+def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "cmovnp\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
+ X86_COND_NP, EFLAGS))]>,
+ TB, OpSize;
+} // Uses = [EFLAGS]
+
// unary instructions
-def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst",
- [(set R8:$dst, (ineg R8:$src))]>;
-def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst",
- [(set R16:$dst, (ineg R16:$src))]>, OpSize;
-def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst",
- [(set R32:$dst, (ineg R32:$src))]>;
+let CodeSize = 2 in {
+let Defs = [EFLAGS] in {
+def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
+ [(set GR8:$dst, (ineg GR8:$src))]>;
+def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
+ [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
+def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
+ [(set GR32:$dst, (ineg GR32:$src))]>;
let isTwoAddress = 0 in {
- def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst",
+ def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
[(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
- def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst",
+ def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
[(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
- def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst",
+ def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
[(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
}
-
-def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst",
- [(set R8:$dst, (not R8:$src))]>;
-def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst",
- [(set R16:$dst, (not R16:$src))]>, OpSize;
-def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst",
- [(set R32:$dst, (not R32:$src))]>;
+} // Defs = [EFLAGS]
+
+def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
+ [(set GR8:$dst, (not GR8:$src))]>;
+def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
+ [(set GR16:$dst, (not GR16:$src))]>, OpSize;
+def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
+ [(set GR32:$dst, (not GR32:$src))]>;
let isTwoAddress = 0 in {
- def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst",
+ def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
[(store (not (loadi8 addr:$dst)), addr:$dst)]>;
- def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst",
+ def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
[(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
- def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst",
+ def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
[(store (not (loadi32 addr:$dst)), addr:$dst)]>;
}
+} // CodeSize
// TODO: inc/dec is slow for P4, but fast for Pentium-M.
-def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst",
- [(set R8:$dst, (add R8:$src, 1))]>;
-let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
-def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst",
- [(set R16:$dst, (add R16:$src, 1))]>, OpSize;
-def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst",
- [(set R32:$dst, (add R32:$src, 1))]>;
+let Defs = [EFLAGS] in {
+let CodeSize = 2 in
+def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
+ [(set GR8:$dst, (add GR8:$src, 1))]>;
+let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
+def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
+ [(set GR16:$dst, (add GR16:$src, 1))]>,
+ OpSize, Requires<[In32BitMode]>;
+def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
+ [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
}
-let isTwoAddress = 0 in {
- def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
+let isTwoAddress = 0, CodeSize = 2 in {
+ def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
[(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
- def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst",
- [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
- def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst",
- [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
+ def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
+ [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
+ OpSize, Requires<[In32BitMode]>;
+ def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
+ [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
+ Requires<[In32BitMode]>;
}
-def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst",
- [(set R8:$dst, (add R8:$src, -1))]>;
-let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
-def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst",
- [(set R16:$dst, (add R16:$src, -1))]>, OpSize;
-def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst",
- [(set R32:$dst, (add R32:$src, -1))]>;
+let CodeSize = 2 in
+def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
+ [(set GR8:$dst, (add GR8:$src, -1))]>;
+let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
+def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
+ [(set GR16:$dst, (add GR16:$src, -1))]>,
+ OpSize, Requires<[In32BitMode]>;
+def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
+ [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
}
-let isTwoAddress = 0 in {
- def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst",
+let isTwoAddress = 0, CodeSize = 2 in {
+ def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
[(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
- def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst",
- [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
- def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst",
- [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
+ def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
+ [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
+ OpSize, Requires<[In32BitMode]>;
+ def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
+ [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
+ Requires<[In32BitMode]>;
}
+} // Defs = [EFLAGS]
// Logical operators...
+let Defs = [EFLAGS] in {
let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
def AND8rr : I<0x20, MRMDestReg,
- (ops R8 :$dst, R8 :$src1, R8 :$src2),
- "and{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
+ (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
+ "and{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
def AND16rr : I<0x21, MRMDestReg,
- (ops R16:$dst, R16:$src1, R16:$src2),
- "and{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (and R16:$src1, R16:$src2))]>, OpSize;
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "and{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
def AND32rr : I<0x21, MRMDestReg,
- (ops R32:$dst, R32:$src1, R32:$src2),
- "and{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (and R32:$src1, R32:$src2))]>;
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "and{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
}
def AND8rm : I<0x22, MRMSrcMem,
- (ops R8 :$dst, R8 :$src1, i8mem :$src2),
- "and{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (and R8:$src1, (load addr:$src2)))]>;
+ (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
+ "and{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
def AND16rm : I<0x23, MRMSrcMem,
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "and{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (and R16:$src1, (load addr:$src2)))]>, OpSize;
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "and{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
def AND32rm : I<0x23, MRMSrcMem,
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "and{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (and R32:$src1, (load addr:$src2)))]>;
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "and{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
def AND8ri : Ii8<0x80, MRM4r,
- (ops R8 :$dst, R8 :$src1, i8imm :$src2),
- "and{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (and R8:$src1, imm:$src2))]>;
+ (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
+ "and{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
def AND16ri : Ii16<0x81, MRM4r,
- (ops R16:$dst, R16:$src1, i16imm:$src2),
- "and{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (and R16:$src1, imm:$src2))]>, OpSize;
+ (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "and{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
def AND32ri : Ii32<0x81, MRM4r,
- (ops R32:$dst, R32:$src1, i32imm:$src2),
- "and{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (and R32:$src1, imm:$src2))]>;
+ (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
+ "and{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
def AND16ri8 : Ii8<0x83, MRM4r,
- (ops R16:$dst, R16:$src1, i16i8imm:$src2),
- "and{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (and R16:$src1, i16immSExt8:$src2))]>,
+ (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
+ "and{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
OpSize;
def AND32ri8 : Ii8<0x83, MRM4r,
- (ops R32:$dst, R32:$src1, i32i8imm:$src2),
- "and{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (and R32:$src1, i32immSExt8:$src2))]>;
+ (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
+ "and{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in {
def AND8mr : I<0x20, MRMDestMem,
- (ops i8mem :$dst, R8 :$src),
- "and{b} {$src, $dst|$dst, $src}",
- [(store (and (load addr:$dst), R8:$src), addr:$dst)]>;
+ (outs), (ins i8mem :$dst, GR8 :$src),
+ "and{b}\t{$src, $dst|$dst, $src}",
+ [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
def AND16mr : I<0x21, MRMDestMem,
- (ops i16mem:$dst, R16:$src),
- "and{w} {$src, $dst|$dst, $src}",
- [(store (and (load addr:$dst), R16:$src), addr:$dst)]>,
+ (outs), (ins i16mem:$dst, GR16:$src),
+ "and{w}\t{$src, $dst|$dst, $src}",
+ [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
OpSize;
def AND32mr : I<0x21, MRMDestMem,
- (ops i32mem:$dst, R32:$src),
- "and{l} {$src, $dst|$dst, $src}",
- [(store (and (load addr:$dst), R32:$src), addr:$dst)]>;
+ (outs), (ins i32mem:$dst, GR32:$src),
+ "and{l}\t{$src, $dst|$dst, $src}",
+ [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
def AND8mi : Ii8<0x80, MRM4m,
- (ops i8mem :$dst, i8imm :$src),
- "and{b} {$src, $dst|$dst, $src}",
+ (outs), (ins i8mem :$dst, i8imm :$src),
+ "and{b}\t{$src, $dst|$dst, $src}",
[(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
def AND16mi : Ii16<0x81, MRM4m,
- (ops i16mem:$dst, i16imm:$src),
- "and{w} {$src, $dst|$dst, $src}",
+ (outs), (ins i16mem:$dst, i16imm:$src),
+ "and{w}\t{$src, $dst|$dst, $src}",
[(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
OpSize;
def AND32mi : Ii32<0x81, MRM4m,
- (ops i32mem:$dst, i32imm:$src),
- "and{l} {$src, $dst|$dst, $src}",
+ (outs), (ins i32mem:$dst, i32imm:$src),
+ "and{l}\t{$src, $dst|$dst, $src}",
[(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
def AND16mi8 : Ii8<0x83, MRM4m,
- (ops i16mem:$dst, i16i8imm :$src),
- "and{w} {$src, $dst|$dst, $src}",
+ (outs), (ins i16mem:$dst, i16i8imm :$src),
+ "and{w}\t{$src, $dst|$dst, $src}",
[(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
OpSize;
def AND32mi8 : Ii8<0x83, MRM4m,
- (ops i32mem:$dst, i32i8imm :$src),
- "and{l} {$src, $dst|$dst, $src}",
- [(store (add (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
+ (outs), (ins i32mem:$dst, i32i8imm :$src),
+ "and{l}\t{$src, $dst|$dst, $src}",
+ [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
}
let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
-def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
- "or{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (or R8:$src1, R8:$src2))]>;
-def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
- "or{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (or R16:$src1, R16:$src2))]>, OpSize;
-def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "or{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (or R32:$src1, R32:$src2))]>;
+def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
+ "or{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
+def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "or{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
+def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "or{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
}
-def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2),
- "or{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (or R8:$src1, (load addr:$src2)))]>;
-def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2),
- "or{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (or R16:$src1, (load addr:$src2)))]>, OpSize;
-def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
- "or{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (or R32:$src1, (load addr:$src2)))]>;
-
-def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
- "or{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (or R8:$src1, imm:$src2))]>;
-def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
- "or{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (or R16:$src1, imm:$src2))]>, OpSize;
-def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
- "or{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (or R32:$src1, imm:$src2))]>;
-
-def OR16ri8 : Ii8<0x83, MRM1r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
- "or{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (or R16:$src1, i16immSExt8:$src2))]>, OpSize;
-def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
- "or{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (or R32:$src1, i32immSExt8:$src2))]>;
+def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
+ "or{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
+def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "or{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
+def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "or{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
+
+def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
+ "or{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
+def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "or{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
+def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
+ "or{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
+
+def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
+ "or{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
+def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
+ "or{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in {
- def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src),
- "or{b} {$src, $dst|$dst, $src}",
- [(store (or (load addr:$dst), R8:$src), addr:$dst)]>;
- def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src),
- "or{w} {$src, $dst|$dst, $src}",
- [(store (or (load addr:$dst), R16:$src), addr:$dst)]>, OpSize;
- def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src),
- "or{l} {$src, $dst|$dst, $src}",
- [(store (or (load addr:$dst), R32:$src), addr:$dst)]>;
- def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
- "or{b} {$src, $dst|$dst, $src}",
+ def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
+ "or{b}\t{$src, $dst|$dst, $src}",
+ [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
+ def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
+ "or{w}\t{$src, $dst|$dst, $src}",
+ [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
+ def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+ "or{l}\t{$src, $dst|$dst, $src}",
+ [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
+ def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
+ "or{b}\t{$src, $dst|$dst, $src}",
[(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
- def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
- "or{w} {$src, $dst|$dst, $src}",
+ def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
+ "or{w}\t{$src, $dst|$dst, $src}",
[(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
OpSize;
- def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
- "or{l} {$src, $dst|$dst, $src}",
+ def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
+ "or{l}\t{$src, $dst|$dst, $src}",
[(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
- def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src),
- "or{w} {$src, $dst|$dst, $src}",
+ def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
+ "or{w}\t{$src, $dst|$dst, $src}",
[(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
OpSize;
- def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src),
- "or{l} {$src, $dst|$dst, $src}",
+ def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
+ "or{l}\t{$src, $dst|$dst, $src}",
[(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
}
let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
def XOR8rr : I<0x30, MRMDestReg,
- (ops R8 :$dst, R8 :$src1, R8 :$src2),
- "xor{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (xor R8:$src1, R8:$src2))]>;
+ (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
+ "xor{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
def XOR16rr : I<0x31, MRMDestReg,
- (ops R16:$dst, R16:$src1, R16:$src2),
- "xor{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (xor R16:$src1, R16:$src2))]>, OpSize;
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "xor{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
def XOR32rr : I<0x31, MRMDestReg,
- (ops R32:$dst, R32:$src1, R32:$src2),
- "xor{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (xor R32:$src1, R32:$src2))]>;
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "xor{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
}
def XOR8rm : I<0x32, MRMSrcMem ,
- (ops R8 :$dst, R8:$src1, i8mem :$src2),
- "xor{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (xor R8:$src1, (load addr:$src2)))]>;
+ (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
+ "xor{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
def XOR16rm : I<0x33, MRMSrcMem ,
- (ops R16:$dst, R16:$src1, i16mem:$src2),
- "xor{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (xor R16:$src1, (load addr:$src2)))]>, OpSize;
+ (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "xor{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
def XOR32rm : I<0x33, MRMSrcMem ,
- (ops R32:$dst, R32:$src1, i32mem:$src2),
- "xor{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (xor R32:$src1, (load addr:$src2)))]>;
+ (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "xor{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
def XOR8ri : Ii8<0x80, MRM6r,
- (ops R8:$dst, R8:$src1, i8imm:$src2),
- "xor{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (xor R8:$src1, imm:$src2))]>;
+ (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+ "xor{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
def XOR16ri : Ii16<0x81, MRM6r,
- (ops R16:$dst, R16:$src1, i16imm:$src2),
- "xor{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (xor R16:$src1, imm:$src2))]>, OpSize;
+ (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "xor{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
def XOR32ri : Ii32<0x81, MRM6r,
- (ops R32:$dst, R32:$src1, i32imm:$src2),
- "xor{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (xor R32:$src1, imm:$src2))]>;
+ (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
+ "xor{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
def XOR16ri8 : Ii8<0x83, MRM6r,
- (ops R16:$dst, R16:$src1, i16i8imm:$src2),
- "xor{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (xor R16:$src1, i16immSExt8:$src2))]>,
+ (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
+ "xor{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
OpSize;
def XOR32ri8 : Ii8<0x83, MRM6r,
- (ops R32:$dst, R32:$src1, i32i8imm:$src2),
- "xor{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (xor R32:$src1, i32immSExt8:$src2))]>;
+ (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
+ "xor{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in {
def XOR8mr : I<0x30, MRMDestMem,
- (ops i8mem :$dst, R8 :$src),
- "xor{b} {$src, $dst|$dst, $src}",
- [(store (xor (load addr:$dst), R8:$src), addr:$dst)]>;
+ (outs), (ins i8mem :$dst, GR8 :$src),
+ "xor{b}\t{$src, $dst|$dst, $src}",
+ [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
def XOR16mr : I<0x31, MRMDestMem,
- (ops i16mem:$dst, R16:$src),
- "xor{w} {$src, $dst|$dst, $src}",
- [(store (xor (load addr:$dst), R16:$src), addr:$dst)]>,
+ (outs), (ins i16mem:$dst, GR16:$src),
+ "xor{w}\t{$src, $dst|$dst, $src}",
+ [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
OpSize;
def XOR32mr : I<0x31, MRMDestMem,
- (ops i32mem:$dst, R32:$src),
- "xor{l} {$src, $dst|$dst, $src}",
- [(store (xor (load addr:$dst), R32:$src), addr:$dst)]>;
+ (outs), (ins i32mem:$dst, GR32:$src),
+ "xor{l}\t{$src, $dst|$dst, $src}",
+ [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
def XOR8mi : Ii8<0x80, MRM6m,
- (ops i8mem :$dst, i8imm :$src),
- "xor{b} {$src, $dst|$dst, $src}",
+ (outs), (ins i8mem :$dst, i8imm :$src),
+ "xor{b}\t{$src, $dst|$dst, $src}",
[(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
def XOR16mi : Ii16<0x81, MRM6m,
- (ops i16mem:$dst, i16imm:$src),
- "xor{w} {$src, $dst|$dst, $src}",
+ (outs), (ins i16mem:$dst, i16imm:$src),
+ "xor{w}\t{$src, $dst|$dst, $src}",
[(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
OpSize;
def XOR32mi : Ii32<0x81, MRM6m,
- (ops i32mem:$dst, i32imm:$src),
- "xor{l} {$src, $dst|$dst, $src}",
+ (outs), (ins i32mem:$dst, i32imm:$src),
+ "xor{l}\t{$src, $dst|$dst, $src}",
[(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
def XOR16mi8 : Ii8<0x83, MRM6m,
- (ops i16mem:$dst, i16i8imm :$src),
- "xor{w} {$src, $dst|$dst, $src}",
+ (outs), (ins i16mem:$dst, i16i8imm :$src),
+ "xor{w}\t{$src, $dst|$dst, $src}",
[(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
OpSize;
def XOR32mi8 : Ii8<0x83, MRM6m,
- (ops i32mem:$dst, i32i8imm :$src),
- "xor{l} {$src, $dst|$dst, $src}",
+ (outs), (ins i32mem:$dst, i32i8imm :$src),
+ "xor{l}\t{$src, $dst|$dst, $src}",
[(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
}
+} // Defs = [EFLAGS]
// Shift instructions
-// FIXME: provide shorter instructions when imm8 == 1
-def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
- "shl{b} {%cl, $dst|$dst, %CL}",
- [(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
-def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src),
- "shl{w} {%cl, $dst|$dst, %CL}",
- [(set R16:$dst, (shl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
-def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src),
- "shl{l} {%cl, $dst|$dst, %CL}",
- [(set R32:$dst, (shl R32:$src, CL))]>, Imp<[CL],[]>;
-
-def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
- "shl{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (shl R8:$src1, (i8 imm:$src2)))]>;
+let Defs = [EFLAGS] in {
+let Uses = [CL] in {
+def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
+ "shl{b}\t{%cl, $dst|$dst, %CL}",
+ [(set GR8:$dst, (shl GR8:$src, CL))]>;
+def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
+ "shl{w}\t{%cl, $dst|$dst, %CL}",
+ [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
+def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
+ "shl{l}\t{%cl, $dst|$dst, %CL}",
+ [(set GR32:$dst, (shl GR32:$src, CL))]>;
+}
+
+def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
+ "shl{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
-def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "shl{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (shl R16:$src1, (i8 imm:$src2)))]>, OpSize;
-def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "shl{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (shl R32:$src1, (i8 imm:$src2)))]>;
+def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
+ "shl{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
+def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
+ "shl{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
}
+// Shift left by one. Not used because (add x, x) is slightly cheaper.
+def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
+ "shl{b}\t$dst", []>;
+def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
+ "shl{w}\t$dst", []>, OpSize;
+def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
+ "shl{l}\t$dst", []>;
+
let isTwoAddress = 0 in {
- def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
- "shl{b} {%cl, $dst|$dst, %CL}",
- [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>;
- def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
- "shl{w} {%cl, $dst|$dst, %CL}",
- [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>, OpSize;
- def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
- "shl{l} {%cl, $dst|$dst, %CL}",
- [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>;
- def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
- "shl{b} {$src, $dst|$dst, $src}",
+ let Uses = [CL] in {
+ def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
+ "shl{b}\t{%cl, $dst|$dst, %CL}",
+ [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
+ def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
+ "shl{w}\t{%cl, $dst|$dst, %CL}",
+ [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
+ def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
+ "shl{l}\t{%cl, $dst|$dst, %CL}",
+ [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
+ }
+ def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
+ "shl{b}\t{$src, $dst|$dst, $src}",
[(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
- def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
- "shl{w} {$src, $dst|$dst, $src}",
+ def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
+ "shl{w}\t{$src, $dst|$dst, $src}",
[(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
OpSize;
- def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
- "shl{l} {$src, $dst|$dst, $src}",
+ def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
+ "shl{l}\t{$src, $dst|$dst, $src}",
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Shift by 1
+ def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
+ "shl{b}\t$dst",
+ [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
+ "shl{w}\t$dst",
+ [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
+ "shl{l}\t$dst",
+ [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
+}
+
+let Uses = [CL] in {
+def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
+ "shr{b}\t{%cl, $dst|$dst, %CL}",
+ [(set GR8:$dst, (srl GR8:$src, CL))]>;
+def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
+ "shr{w}\t{%cl, $dst|$dst, %CL}",
+ [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
+def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
+ "shr{l}\t{%cl, $dst|$dst, %CL}",
+ [(set GR32:$dst, (srl GR32:$src, CL))]>;
}
-def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src),
- "shr{b} {%cl, $dst|$dst, %CL}",
- [(set R8:$dst, (srl R8:$src, CL))]>, Imp<[CL],[]>;
-def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src),
- "shr{w} {%cl, $dst|$dst, %CL}",
- [(set R16:$dst, (srl R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
-def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src),
- "shr{l} {%cl, $dst|$dst, %CL}",
- [(set R32:$dst, (srl R32:$src, CL))]>, Imp<[CL],[]>;
-
-def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
- "shr{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (srl R8:$src1, (i8 imm:$src2)))]>;
-def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "shr{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (srl R16:$src1, (i8 imm:$src2)))]>, OpSize;
-def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "shr{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (srl R32:$src1, (i8 imm:$src2)))]>;
+def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+ "shr{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
+def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
+ "shr{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
+def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
+ "shr{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
+
+// Shift by 1
+def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
+ "shr{b}\t$dst",
+ [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
+def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
+ "shr{w}\t$dst",
+ [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
+def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
+ "shr{l}\t$dst",
+ [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
let isTwoAddress = 0 in {
- def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
- "shr{b} {%cl, $dst|$dst, %CL}",
- [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>;
- def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
- "shr{w} {%cl, $dst|$dst, %CL}",
+ let Uses = [CL] in {
+ def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
+ "shr{b}\t{%cl, $dst|$dst, %CL}",
+ [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
+ def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
+ "shr{w}\t{%cl, $dst|$dst, %CL}",
[(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>, OpSize;
- def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
- "shr{l} {%cl, $dst|$dst, %CL}",
- [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>;
- def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
- "shr{b} {$src, $dst|$dst, $src}",
+ OpSize;
+ def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
+ "shr{l}\t{%cl, $dst|$dst, %CL}",
+ [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
+ }
+ def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
+ "shr{b}\t{$src, $dst|$dst, $src}",
[(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
- def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
- "shr{w} {$src, $dst|$dst, $src}",
+ def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
+ "shr{w}\t{$src, $dst|$dst, $src}",
[(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
OpSize;
- def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
- "shr{l} {$src, $dst|$dst, $src}",
+ def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
+ "shr{l}\t{$src, $dst|$dst, $src}",
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Shift by 1
+ def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
+ "shr{b}\t$dst",
+ [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
+ "shr{w}\t$dst",
+ [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
+ def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
+ "shr{l}\t$dst",
+ [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
-def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src),
- "sar{b} {%cl, $dst|$dst, %CL}",
- [(set R8:$dst, (sra R8:$src, CL))]>, Imp<[CL],[]>;
-def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src),
- "sar{w} {%cl, $dst|$dst, %CL}",
- [(set R16:$dst, (sra R16:$src, CL))]>, Imp<[CL],[]>, OpSize;
-def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src),
- "sar{l} {%cl, $dst|$dst, %CL}",
- [(set R32:$dst, (sra R32:$src, CL))]>, Imp<[CL],[]>;
-
-def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
- "sar{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (sra R8:$src1, (i8 imm:$src2)))]>;
-def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "sar{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (sra R16:$src1, (i8 imm:$src2)))]>,
+let Uses = [CL] in {
+def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
+ "sar{b}\t{%cl, $dst|$dst, %CL}",
+ [(set GR8:$dst, (sra GR8:$src, CL))]>;
+def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
+ "sar{w}\t{%cl, $dst|$dst, %CL}",
+ [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
+def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
+ "sar{l}\t{%cl, $dst|$dst, %CL}",
+ [(set GR32:$dst, (sra GR32:$src, CL))]>;
+}
+
+def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
+ "sar{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
+def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
+ "sar{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
OpSize;
-def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "sar{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (sra R32:$src1, (i8 imm:$src2)))]>;
+def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
+ "sar{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
+
+// Shift by 1
+def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
+ "sar{b}\t$dst",
+ [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
+def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
+ "sar{w}\t$dst",
+ [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
+def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
+ "sar{l}\t$dst",
+ [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
+
let isTwoAddress = 0 in {
- def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
- "sar{b} {%cl, $dst|$dst, %CL}",
- [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>;
- def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
- "sar{w} {%cl, $dst|$dst, %CL}",
- [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>, OpSize;
- def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
- "sar{l} {%cl, $dst|$dst, %CL}",
- [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
- Imp<[CL],[]>;
- def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
- "sar{b} {$src, $dst|$dst, $src}",
+ let Uses = [CL] in {
+ def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
+ "sar{b}\t{%cl, $dst|$dst, %CL}",
+ [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
+ def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
+ "sar{w}\t{%cl, $dst|$dst, %CL}",
+ [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
+ def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
+ "sar{l}\t{%cl, $dst|$dst, %CL}",
+ [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
+ }
+ def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
+ "sar{b}\t{$src, $dst|$dst, $src}",
[(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
- def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
- "sar{w} {$src, $dst|$dst, $src}",
+ def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
+ "sar{w}\t{$src, $dst|$dst, $src}",
[(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
OpSize;
- def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
- "sar{l} {$src, $dst|$dst, $src}",
+ def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
+ "sar{l}\t{$src, $dst|$dst, $src}",
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Shift by 1
+ def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
+ "sar{b}\t$dst",
+ [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
+ "sar{w}\t$dst",
+ [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
+ "sar{l}\t$dst",
+ [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
// Rotate instructions
// FIXME: provide shorter instructions when imm8 == 1
-def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src),
- "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
-def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src),
- "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
-def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src),
- "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
-
-def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
- "rol{b} {$src2, $dst|$dst, $src2}", []>;
-def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "rol{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
-def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "rol{l} {$src2, $dst|$dst, $src2}", []>;
+let Uses = [CL] in {
+def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
+ "rol{b}\t{%cl, $dst|$dst, %CL}",
+ [(set GR8:$dst, (rotl GR8:$src, CL))]>;
+def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
+ "rol{w}\t{%cl, $dst|$dst, %CL}",
+ [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
+def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
+ "rol{l}\t{%cl, $dst|$dst, %CL}",
+ [(set GR32:$dst, (rotl GR32:$src, CL))]>;
+}
+
+def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
+ "rol{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
+def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
+ "rol{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
+def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
+ "rol{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
+
+// Rotate by 1
+def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
+ "rol{b}\t$dst",
+ [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
+def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
+ "rol{w}\t$dst",
+ [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
+def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
+ "rol{l}\t$dst",
+ [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
let isTwoAddress = 0 in {
- def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
- "rol{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
- def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
- "rol{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
- def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
- "rol{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
- def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
- "rol{b} {$src, $dst|$dst, $src}", []>;
- def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
- "rol{w} {$src, $dst|$dst, $src}", []>, OpSize;
- def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
- "rol{l} {$src, $dst|$dst, $src}", []>;
+ let Uses = [CL] in {
+ def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
+ "rol{b}\t{%cl, $dst|$dst, %CL}",
+ [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
+ def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
+ "rol{w}\t{%cl, $dst|$dst, %CL}",
+ [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
+ def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
+ "rol{l}\t{%cl, $dst|$dst, %CL}",
+ [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
+ }
+ def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
+ "rol{b}\t{$src, $dst|$dst, $src}",
+ [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+ def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
+ "rol{w}\t{$src, $dst|$dst, $src}",
+ [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
+ OpSize;
+ def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
+ "rol{l}\t{$src, $dst|$dst, $src}",
+ [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Rotate by 1
+ def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
+ "rol{b}\t$dst",
+ [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
+ "rol{w}\t$dst",
+ [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
+ "rol{l}\t$dst",
+ [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
+}
+
+let Uses = [CL] in {
+def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
+ "ror{b}\t{%cl, $dst|$dst, %CL}",
+ [(set GR8:$dst, (rotr GR8:$src, CL))]>;
+def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
+ "ror{w}\t{%cl, $dst|$dst, %CL}",
+ [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
+def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
+ "ror{l}\t{%cl, $dst|$dst, %CL}",
+ [(set GR32:$dst, (rotr GR32:$src, CL))]>;
}
-def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src),
- "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
-def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src),
- "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
-def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src),
- "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
-
-def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
- "ror{b} {$src2, $dst|$dst, $src2}", []>;
-def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "ror{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
-def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "ror{l} {$src2, $dst|$dst, $src2}", []>;
+def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
+ "ror{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
+def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
+ "ror{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
+def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
+ "ror{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
+
+// Rotate by 1
+def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
+ "ror{b}\t$dst",
+ [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
+def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
+ "ror{w}\t$dst",
+ [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
+def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
+ "ror{l}\t$dst",
+ [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
+
let isTwoAddress = 0 in {
- def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
- "ror{b} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
- def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
- "ror{w} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>, OpSize;
- def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
- "ror{l} {%cl, $dst|$dst, %CL}", []>, Imp<[CL],[]>;
- def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
- "ror{b} {$src, $dst|$dst, $src}", []>;
- def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
- "ror{w} {$src, $dst|$dst, $src}", []>, OpSize;
- def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
- "ror{l} {$src, $dst|$dst, $src}", []>;
+ let Uses = [CL] in {
+ def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
+ "ror{b}\t{%cl, $dst|$dst, %CL}",
+ [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
+ def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
+ "ror{w}\t{%cl, $dst|$dst, %CL}",
+ [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
+ def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
+ "ror{l}\t{%cl, $dst|$dst, %CL}",
+ [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
+ }
+ def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
+ "ror{b}\t{$src, $dst|$dst, $src}",
+ [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+ def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
+ "ror{w}\t{$src, $dst|$dst, $src}",
+ [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
+ OpSize;
+ def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
+ "ror{l}\t{$src, $dst|$dst, $src}",
+ [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Rotate by 1
+ def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
+ "ror{b}\t$dst",
+ [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
+ "ror{w}\t$dst",
+ [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
+ "ror{l}\t$dst",
+ [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
// Double shift instructions (generalizations of rotate)
-
-def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
- Imp<[CL],[]>, TB;
-def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
- Imp<[CL],[]>, TB;
-def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
- "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
- Imp<[CL],[]>, TB, OpSize;
-def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
- "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
- Imp<[CL],[]>, TB, OpSize;
+let Uses = [CL] in {
+def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
+def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
+def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
+ TB, OpSize;
+def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
+ TB, OpSize;
+}
let isCommutable = 1 in { // These instructions commute to each other.
def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
- (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
- "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB;
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
+ "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
+ (i8 imm:$src3)))]>,
+ TB;
def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
- (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3),
- "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>, TB;
+ (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
+ "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
+ (i8 imm:$src3)))]>,
+ TB;
def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
- (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
- "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
+ "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
+ (i8 imm:$src3)))]>,
TB, OpSize;
def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
- (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3),
- "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
+ "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
+ (i8 imm:$src3)))]>,
TB, OpSize;
}
let isTwoAddress = 0 in {
- def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
- Imp<[CL],[]>, TB;
- def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
- Imp<[CL],[]>, TB;
+ let Uses = [CL] in {
+ def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
+ "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
+ addr:$dst)]>, TB;
+ def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
+ "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
+ addr:$dst)]>, TB;
+ }
def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
- (ops i32mem:$dst, R32:$src2, i8imm:$src3),
- "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
+ "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
+ (i8 imm:$src3)), addr:$dst)]>,
TB;
def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
- (ops i32mem:$dst, R32:$src2, i8imm:$src3),
- "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
+ "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
+ (i8 imm:$src3)), addr:$dst)]>,
TB;
- def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2),
- "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
- Imp<[CL],[]>, TB, OpSize;
- def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2),
- "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
- Imp<[CL],[]>, TB, OpSize;
+ let Uses = [CL] in {
+ def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
+ "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
+ addr:$dst)]>, TB, OpSize;
+ def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
+ "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
+ [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
+ addr:$dst)]>, TB, OpSize;
+ }
def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
- (ops i16mem:$dst, R16:$src2, i8imm:$src3),
- "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
+ "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
+ (i8 imm:$src3)), addr:$dst)]>,
TB, OpSize;
def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
- (ops i16mem:$dst, R16:$src2, i8imm:$src3),
- "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
+ (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
+ "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+ [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
+ (i8 imm:$src3)), addr:$dst)]>,
TB, OpSize;
}
+} // Defs = [EFLAGS]
// Arithmetic.
+let Defs = [EFLAGS] in {
let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
-def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
- "add{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (add R8:$src1, R8:$src2))]>;
+def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
+ (ins GR8 :$src1, GR8 :$src2),
+ "add{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
-def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
- "add{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (add R16:$src1, R16:$src2))]>, OpSize;
-def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "add{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (add R32:$src1, R32:$src2))]>;
+def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
+ (ins GR16:$src1, GR16:$src2),
+ "add{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
+def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
+ (ins GR32:$src1, GR32:$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
} // end isConvertibleToThreeAddress
} // end isCommutable
-def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
- "add{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>;
-def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
- "add{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize;
-def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
- "add{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>;
-
-def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
- "add{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (add R8:$src1, imm:$src2))]>;
+def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
+ (ins GR8 :$src1, i8mem :$src2),
+ "add{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
+def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
+ (ins GR16:$src1, i16mem:$src2),
+ "add{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>,OpSize;
+def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
+ (ins GR32:$src1, i32mem:$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
+
+def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+ "add{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
-def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2),
- "add{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (add R16:$src1, imm:$src2))]>, OpSize;
-def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2),
- "add{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (add R32:$src1, imm:$src2))]>;
+def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
+ (ins GR16:$src1, i16imm:$src2),
+ "add{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
+def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
+ (ins GR32:$src1, i32imm:$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
+def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
+ (ins GR16:$src1, i16i8imm:$src2),
+ "add{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>, OpSize;
+def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
+ (ins GR32:$src1, i32i8imm:$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
}
-// FIXME: move ADD16ri8 above ADD16ri to optimize for space.
-def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
- "add{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (add R16:$src1, i16immSExt8:$src2))]>,
- OpSize;
-def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
- "add{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (add R32:$src1, i32immSExt8:$src2))]>;
-
let isTwoAddress = 0 in {
- def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
- "add{b} {$src2, $dst|$dst, $src2}",
- [(store (add (load addr:$dst), R8:$src2), addr:$dst)]>;
- def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2),
- "add{w} {$src2, $dst|$dst, $src2}",
- [(store (add (load addr:$dst), R16:$src2), addr:$dst)]>,
- OpSize;
- def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "add{l} {$src2, $dst|$dst, $src2}",
- [(store (add (load addr:$dst), R32:$src2), addr:$dst)]>;
- def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
- "add{b} {$src2, $dst|$dst, $src2}",
+ def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
+ "add{b}\t{$src2, $dst|$dst, $src2}",
+ [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
+ def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
+ "add{w}\t{$src2, $dst|$dst, $src2}",
+ [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
+ OpSize;
+ def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}",
+ [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
+ def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
+ "add{b}\t{$src2, $dst|$dst, $src2}",
[(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
- def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
- "add{w} {$src2, $dst|$dst, $src2}",
+ def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
+ "add{w}\t{$src2, $dst|$dst, $src2}",
[(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
- OpSize;
- def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
- "add{l} {$src2, $dst|$dst, $src2}",
+ OpSize;
+ def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}",
[(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
- def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
- "add{w} {$src2, $dst|$dst, $src2}",
+ def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
+ "add{w}\t{$src2, $dst|$dst, $src2}",
[(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
- OpSize;
- def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
- "add{l} {$src2, $dst|$dst, $src2}",
+ OpSize;
+ def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
+ "add{l}\t{$src2, $dst|$dst, $src2}",
[(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
+let Uses = [EFLAGS] in {
let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
-def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
+def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "adc{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
}
-def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
-def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
-def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
+def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "adc{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
+def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
+ "adc{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
+def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
+ "adc{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in {
- def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
- def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
- def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2),
- "adc{l} {$src2, $dst|$dst, $src2}", []>;
+ def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
+ "adc{l}\t{$src2, $dst|$dst, $src2}",
+ [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
+ def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
+ "adc{l}\t{$src2, $dst|$dst, $src2}",
+ [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
+ def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
+ "adc{l}\t{$src2, $dst|$dst, $src2}",
+ [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
-
-def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
- "sub{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (sub R8:$src1, R8:$src2))]>;
-def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
- "sub{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (sub R16:$src1, R16:$src2))]>, OpSize;
-def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "sub{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (sub R32:$src1, R32:$src2))]>;
-def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
- "sub{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (sub R8:$src1, (load addr:$src2)))]>;
-def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
- "sub{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (sub R16:$src1, (load addr:$src2)))]>, OpSize;
-def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
- "sub{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (sub R32:$src1, (load addr:$src2)))]>;
-
-def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
- "sub{b} {$src2, $dst|$dst, $src2}",
- [(set R8:$dst, (sub R8:$src1, imm:$src2))]>;
-def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
- "sub{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (sub R16:$src1, imm:$src2))]>, OpSize;
-def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
- "sub{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (sub R32:$src1, imm:$src2))]>;
-def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i16i8imm:$src2),
- "sub{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (sub R16:$src1, i16immSExt8:$src2))]>,
- OpSize;
-def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i32i8imm:$src2),
- "sub{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (sub R32:$src1, i32immSExt8:$src2))]>;
+} // Uses = [EFLAGS]
+
+def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
+ "sub{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
+def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "sub{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
+def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "sub{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
+def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
+ "sub{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
+def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "sub{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
+def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "sub{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
+
+def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
+ "sub{b}\t{$src2, $dst|$dst, $src2}",
+ [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
+def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "sub{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
+def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
+ "sub{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
+def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
+ "sub{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
+ OpSize;
+def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
+ "sub{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
let isTwoAddress = 0 in {
- def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2),
- "sub{b} {$src2, $dst|$dst, $src2}",
- [(store (sub (load addr:$dst), R8:$src2), addr:$dst)]>;
- def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2),
- "sub{w} {$src2, $dst|$dst, $src2}",
- [(store (sub (load addr:$dst), R16:$src2), addr:$dst)]>,
- OpSize;
- def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "sub{l} {$src2, $dst|$dst, $src2}",
- [(store (sub (load addr:$dst), R32:$src2), addr:$dst)]>;
- def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
- "sub{b} {$src2, $dst|$dst, $src2}",
+ def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
+ "sub{b}\t{$src2, $dst|$dst, $src2}",
+ [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
+ def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
+ "sub{w}\t{$src2, $dst|$dst, $src2}",
+ [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
+ OpSize;
+ def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
+ "sub{l}\t{$src2, $dst|$dst, $src2}",
+ [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
+ def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
+ "sub{b}\t{$src2, $dst|$dst, $src2}",
[(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
- def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
- "sub{w} {$src2, $dst|$dst, $src2}",
+ def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
+ "sub{w}\t{$src2, $dst|$dst, $src2}",
[(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
- OpSize;
- def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
- "sub{l} {$src2, $dst|$dst, $src2}",
+ OpSize;
+ def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
+ "sub{l}\t{$src2, $dst|$dst, $src2}",
[(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
- def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
- "sub{w} {$src2, $dst|$dst, $src2}",
+ def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
+ "sub{w}\t{$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
- OpSize;
- def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
- "sub{l} {$src2, $dst|$dst, $src2}",
+ OpSize;
+ def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
+ "sub{l}\t{$src2, $dst|$dst, $src2}",
[(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
-def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
+let Uses = [EFLAGS] in {
+def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "sbb{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
let isTwoAddress = 0 in {
- def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
- def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
- "sbb{b} {$src2, $dst|$dst, $src2}", []>;
- def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
- def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
- def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
- def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
+ def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
+ "sbb{l}\t{$src2, $dst|$dst, $src2}",
+ [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
+ def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
+ "sbb{b}\t{$src2, $dst|$dst, $src2}",
+ [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
+ def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
+ "sbb{l}\t{$src2, $dst|$dst, $src2}",
+ [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
+ def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
+ "sbb{l}\t{$src2, $dst|$dst, $src2}",
+ [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
}
-def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
- "sbb{b} {$src2, $dst|$dst, $src2}", []>;
-def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
-
-def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
-def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
-
-def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2),
- "sbb{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
-def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
- "sbb{l} {$src2, $dst|$dst, $src2}", []>;
-
+def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "sbb{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
+def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
+ "sbb{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
+def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
+ "sbb{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
+} // Uses = [EFLAGS]
+} // Defs = [EFLAGS]
+
+let Defs = [EFLAGS] in {
let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
-def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
- "imul{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (mul R16:$src1, R16:$src2))]>, TB, OpSize;
-def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
- "imul{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (mul R32:$src1, R32:$src2))]>, TB;
+def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+ "imul{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
+def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
+ "imul{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
}
-def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
- "imul{w} {$src2, $dst|$dst, $src2}",
- [(set R16:$dst, (mul R16:$src1, (load addr:$src2)))]>,
+def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
+ "imul{w}\t{$src2, $dst|$dst, $src2}",
+ [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
TB, OpSize;
-def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
- "imul{l} {$src2, $dst|$dst, $src2}",
- [(set R32:$dst, (mul R32:$src1, (load addr:$src2)))]>, TB;
-
+def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
+ "imul{l}\t{$src2, $dst|$dst, $src2}",
+ [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
+} // Defs = [EFLAGS]
} // end Two Address instructions
// Suprisingly enough, these are not two address instructions!
-def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16
- (ops R16:$dst, R16:$src1, i16imm:$src2),
- "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set R16:$dst, (mul R16:$src1, imm:$src2))]>, OpSize;
-def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32
- (ops R32:$dst, R32:$src1, i32imm:$src2),
- "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set R32:$dst, (mul R32:$src1, imm:$src2))]>;
-def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8
- (ops R16:$dst, R16:$src1, i16i8imm:$src2),
- "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set R16:$dst, (mul R16:$src1, i16immSExt8:$src2))]>,
+let Defs = [EFLAGS] in {
+def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
+ (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+ "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
+def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
+ (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
+ "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
+def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
+ (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
+ "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
OpSize;
-def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8
- (ops R32:$dst, R32:$src1, i32i8imm:$src2),
- "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set R32:$dst, (mul R32:$src1, i32immSExt8:$src2))]>;
-
-def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16
- (ops R16:$dst, i16mem:$src1, i16imm:$src2),
- "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set R16:$dst, (mul (load addr:$src1), imm:$src2))]>,
+def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
+ (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
+ "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
+
+def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
+ (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
+ "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
OpSize;
-def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32
- (ops R32:$dst, i32mem:$src1, i32imm:$src2),
- "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set R32:$dst, (mul (load addr:$src1), imm:$src2))]>;
-def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8
- (ops R16:$dst, i16mem:$src1, i16i8imm :$src2),
- "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set R16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
+def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
+ (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
+ "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
+def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
+ (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
+ "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
OpSize;
-def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8
- (ops R32:$dst, i32mem:$src1, i32i8imm: $src2),
- "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
- [(set R32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
+def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
+ (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
+ "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+ [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
+} // Defs = [EFLAGS]
//===----------------------------------------------------------------------===//
// Test instructions are just like AND, except they don't generate a result.
//
+let Defs = [EFLAGS] in {
let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
-def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
- "test{b} {$src2, $src1|$src1, $src2}", []>;
-def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
- "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
-def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
- "test{l} {$src2, $src1|$src1, $src2}", []>;
+def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
+ "test{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR8:$src1, GR8:$src2), 0),
+ (implicit EFLAGS)]>;
+def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
+ "test{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR16:$src1, GR16:$src2), 0),
+ (implicit EFLAGS)]>,
+ OpSize;
+def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
+ "test{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR32:$src1, GR32:$src2), 0),
+ (implicit EFLAGS)]>;
}
-def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2),
- "test{b} {$src2, $src1|$src1, $src2}", []>;
-def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2),
- "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
-def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2),
- "test{l} {$src2, $src1|$src1, $src2}", []>;
-def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2),
- "test{b} {$src2, $src1|$src1, $src2}", []>;
-def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2),
- "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
-def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2),
- "test{l} {$src2, $src1|$src1, $src2}", []>;
-
-def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8
- (ops R8:$src1, i8imm:$src2),
- "test{b} {$src2, $src1|$src1, $src2}", []>;
-def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16
- (ops R16:$src1, i16imm:$src2),
- "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
-def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32
- (ops R32:$src1, i32imm:$src2),
- "test{l} {$src2, $src1|$src1, $src2}", []>;
-def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
- (ops i32mem:$src1, i8imm:$src2),
- "test{b} {$src2, $src1|$src1, $src2}", []>;
-def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
- (ops i16mem:$src1, i16imm:$src2),
- "test{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
-def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
- (ops i32mem:$src1, i32imm:$src2),
- "test{l} {$src2, $src1|$src1, $src2}", []>;
+def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
+ "test{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
+ (implicit EFLAGS)]>;
+def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
+ "test{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
+ (implicit EFLAGS)]>, OpSize;
+def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
+ "test{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
+ (implicit EFLAGS)]>;
+
+def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
+ (outs), (ins GR8:$src1, i8imm:$src2),
+ "test{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR8:$src1, imm:$src2), 0),
+ (implicit EFLAGS)]>;
+def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
+ (outs), (ins GR16:$src1, i16imm:$src2),
+ "test{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR16:$src1, imm:$src2), 0),
+ (implicit EFLAGS)]>, OpSize;
+def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
+ (outs), (ins GR32:$src1, i32imm:$src2),
+ "test{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and GR32:$src1, imm:$src2), 0),
+ (implicit EFLAGS)]>;
+
+def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
+ (outs), (ins i8mem:$src1, i8imm:$src2),
+ "test{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
+ (implicit EFLAGS)]>;
+def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
+ (outs), (ins i16mem:$src1, i16imm:$src2),
+ "test{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
+ (implicit EFLAGS)]>, OpSize;
+def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
+ (outs), (ins i32mem:$src1, i32imm:$src2),
+ "test{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
+ (implicit EFLAGS)]>;
+} // Defs = [EFLAGS]
// Condition code ops, incl. set if equal/not equal/...
-def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
-def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
+let Defs = [EFLAGS], Uses = [AH] in
+def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
+let Defs = [AH], Uses = [EFLAGS] in
+def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
-def SETBr : I<0x92, MRM0r,
- (ops R8 :$dst), "setb $dst", []>, TB; // R8 = < unsign
-def SETBm : I<0x92, MRM0m,
- (ops i8mem:$dst), "setb $dst", []>, TB; // [mem8] = < unsign
-def SETAEr : I<0x93, MRM0r,
- (ops R8 :$dst), "setae $dst", []>, TB; // R8 = >= unsign
-def SETAEm : I<0x93, MRM0m,
- (ops i8mem:$dst), "setae $dst", []>, TB; // [mem8] = >= unsign
+let Uses = [EFLAGS] in {
def SETEr : I<0x94, MRM0r,
- (ops R8 :$dst), "sete $dst", []>, TB; // R8 = ==
+ (outs GR8 :$dst), (ins),
+ "sete\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
+ TB; // GR8 = ==
def SETEm : I<0x94, MRM0m,
- (ops i8mem:$dst), "sete $dst", []>, TB; // [mem8] = ==
+ (outs), (ins i8mem:$dst),
+ "sete\t$dst",
+ [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = ==
def SETNEr : I<0x95, MRM0r,
- (ops R8 :$dst), "setne $dst", []>, TB; // R8 = !=
+ (outs GR8 :$dst), (ins),
+ "setne\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
+ TB; // GR8 = !=
def SETNEm : I<0x95, MRM0m,
- (ops i8mem:$dst), "setne $dst", []>, TB; // [mem8] = !=
+ (outs), (ins i8mem:$dst),
+ "setne\t$dst",
+ [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = !=
+def SETLr : I<0x9C, MRM0r,
+ (outs GR8 :$dst), (ins),
+ "setl\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
+ TB; // GR8 = < signed
+def SETLm : I<0x9C, MRM0m,
+ (outs), (ins i8mem:$dst),
+ "setl\t$dst",
+ [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = < signed
+def SETGEr : I<0x9D, MRM0r,
+ (outs GR8 :$dst), (ins),
+ "setge\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
+ TB; // GR8 = >= signed
+def SETGEm : I<0x9D, MRM0m,
+ (outs), (ins i8mem:$dst),
+ "setge\t$dst",
+ [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = >= signed
+def SETLEr : I<0x9E, MRM0r,
+ (outs GR8 :$dst), (ins),
+ "setle\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
+ TB; // GR8 = <= signed
+def SETLEm : I<0x9E, MRM0m,
+ (outs), (ins i8mem:$dst),
+ "setle\t$dst",
+ [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = <= signed
+def SETGr : I<0x9F, MRM0r,
+ (outs GR8 :$dst), (ins),
+ "setg\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
+ TB; // GR8 = > signed
+def SETGm : I<0x9F, MRM0m,
+ (outs), (ins i8mem:$dst),
+ "setg\t$dst",
+ [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = > signed
+
+def SETBr : I<0x92, MRM0r,
+ (outs GR8 :$dst), (ins),
+ "setb\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
+ TB; // GR8 = < unsign
+def SETBm : I<0x92, MRM0m,
+ (outs), (ins i8mem:$dst),
+ "setb\t$dst",
+ [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = < unsign
+def SETAEr : I<0x93, MRM0r,
+ (outs GR8 :$dst), (ins),
+ "setae\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
+ TB; // GR8 = >= unsign
+def SETAEm : I<0x93, MRM0m,
+ (outs), (ins i8mem:$dst),
+ "setae\t$dst",
+ [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = >= unsign
def SETBEr : I<0x96, MRM0r,
- (ops R8 :$dst), "setbe $dst", []>, TB; // R8 = <= unsign
+ (outs GR8 :$dst), (ins),
+ "setbe\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
+ TB; // GR8 = <= unsign
def SETBEm : I<0x96, MRM0m,
- (ops i8mem:$dst), "setbe $dst", []>, TB; // [mem8] = <= unsign
+ (outs), (ins i8mem:$dst),
+ "setbe\t$dst",
+ [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = <= unsign
def SETAr : I<0x97, MRM0r,
- (ops R8 :$dst), "seta $dst", []>, TB; // R8 = > signed
+ (outs GR8 :$dst), (ins),
+ "seta\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
+ TB; // GR8 = > signed
def SETAm : I<0x97, MRM0m,
- (ops i8mem:$dst), "seta $dst", []>, TB; // [mem8] = > signed
+ (outs), (ins i8mem:$dst),
+ "seta\t$dst",
+ [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = > signed
+
def SETSr : I<0x98, MRM0r,
- (ops R8 :$dst), "sets $dst", []>, TB; // R8 = <sign bit>
+ (outs GR8 :$dst), (ins),
+ "sets\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
+ TB; // GR8 = <sign bit>
def SETSm : I<0x98, MRM0m,
- (ops i8mem:$dst), "sets $dst", []>, TB; // [mem8] = <sign bit>
+ (outs), (ins i8mem:$dst),
+ "sets\t$dst",
+ [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = <sign bit>
def SETNSr : I<0x99, MRM0r,
- (ops R8 :$dst), "setns $dst", []>, TB; // R8 = !<sign bit>
+ (outs GR8 :$dst), (ins),
+ "setns\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
+ TB; // GR8 = !<sign bit>
def SETNSm : I<0x99, MRM0m,
- (ops i8mem:$dst), "setns $dst", []>, TB; // [mem8] = !<sign bit>
+ (outs), (ins i8mem:$dst),
+ "setns\t$dst",
+ [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = !<sign bit>
def SETPr : I<0x9A, MRM0r,
- (ops R8 :$dst), "setp $dst", []>, TB; // R8 = parity
+ (outs GR8 :$dst), (ins),
+ "setp\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
+ TB; // GR8 = parity
def SETPm : I<0x9A, MRM0m,
- (ops i8mem:$dst), "setp $dst", []>, TB; // [mem8] = parity
+ (outs), (ins i8mem:$dst),
+ "setp\t$dst",
+ [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = parity
def SETNPr : I<0x9B, MRM0r,
- (ops R8 :$dst), "setnp $dst", []>, TB; // R8 = not parity
+ (outs GR8 :$dst), (ins),
+ "setnp\t$dst",
+ [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
+ TB; // GR8 = not parity
def SETNPm : I<0x9B, MRM0m,
- (ops i8mem:$dst), "setnp $dst", []>, TB; // [mem8] = not parity
-def SETLr : I<0x9C, MRM0r,
- (ops R8 :$dst), "setl $dst", []>, TB; // R8 = < signed
-def SETLm : I<0x9C, MRM0m,
- (ops i8mem:$dst), "setl $dst", []>, TB; // [mem8] = < signed
-def SETGEr : I<0x9D, MRM0r,
- (ops R8 :$dst), "setge $dst", []>, TB; // R8 = >= signed
-def SETGEm : I<0x9D, MRM0m,
- (ops i8mem:$dst), "setge $dst", []>, TB; // [mem8] = >= signed
-def SETLEr : I<0x9E, MRM0r,
- (ops R8 :$dst), "setle $dst", []>, TB; // R8 = <= signed
-def SETLEm : I<0x9E, MRM0m,
- (ops i8mem:$dst), "setle $dst", []>, TB; // [mem8] = <= signed
-def SETGr : I<0x9F, MRM0r,
- (ops R8 :$dst), "setg $dst", []>, TB; // R8 = < signed
-def SETGm : I<0x9F, MRM0m,
- (ops i8mem:$dst), "setg $dst", []>, TB; // [mem8] = < signed
+ (outs), (ins i8mem:$dst),
+ "setnp\t$dst",
+ [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
+ TB; // [mem8] = not parity
+} // Uses = [EFLAGS]
+
// Integer comparisons
+let Defs = [EFLAGS] in {
def CMP8rr : I<0x38, MRMDestReg,
- (ops R8 :$src1, R8 :$src2),
- "cmp{b} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins GR8 :$src1, GR8 :$src2),
+ "cmp{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
def CMP16rr : I<0x39, MRMDestReg,
- (ops R16:$src1, R16:$src2),
- "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
+ (outs), (ins GR16:$src1, GR16:$src2),
+ "cmp{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
def CMP32rr : I<0x39, MRMDestReg,
- (ops R32:$src1, R32:$src2),
- "cmp{l} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins GR32:$src1, GR32:$src2),
+ "cmp{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
def CMP8mr : I<0x38, MRMDestMem,
- (ops i8mem :$src1, R8 :$src2),
- "cmp{b} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins i8mem :$src1, GR8 :$src2),
+ "cmp{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (loadi8 addr:$src1), GR8:$src2),
+ (implicit EFLAGS)]>;
def CMP16mr : I<0x39, MRMDestMem,
- (ops i16mem:$src1, R16:$src2),
- "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
+ (outs), (ins i16mem:$src1, GR16:$src2),
+ "cmp{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (loadi16 addr:$src1), GR16:$src2),
+ (implicit EFLAGS)]>, OpSize;
def CMP32mr : I<0x39, MRMDestMem,
- (ops i32mem:$src1, R32:$src2),
- "cmp{l} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins i32mem:$src1, GR32:$src2),
+ "cmp{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (loadi32 addr:$src1), GR32:$src2),
+ (implicit EFLAGS)]>;
def CMP8rm : I<0x3A, MRMSrcMem,
- (ops R8 :$src1, i8mem :$src2),
- "cmp{b} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins GR8 :$src1, i8mem :$src2),
+ "cmp{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
+ (implicit EFLAGS)]>;
def CMP16rm : I<0x3B, MRMSrcMem,
- (ops R16:$src1, i16mem:$src2),
- "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
+ (outs), (ins GR16:$src1, i16mem:$src2),
+ "cmp{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
+ (implicit EFLAGS)]>, OpSize;
def CMP32rm : I<0x3B, MRMSrcMem,
- (ops R32:$src1, i32mem:$src2),
- "cmp{l} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins GR32:$src1, i32mem:$src2),
+ "cmp{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
+ (implicit EFLAGS)]>;
def CMP8ri : Ii8<0x80, MRM7r,
- (ops R16:$src1, i8imm:$src2),
- "cmp{b} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins GR8:$src1, i8imm:$src2),
+ "cmp{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
def CMP16ri : Ii16<0x81, MRM7r,
- (ops R16:$src1, i16imm:$src2),
- "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
+ (outs), (ins GR16:$src1, i16imm:$src2),
+ "cmp{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR16:$src1, imm:$src2),
+ (implicit EFLAGS)]>, OpSize;
def CMP32ri : Ii32<0x81, MRM7r,
- (ops R32:$src1, i32imm:$src2),
- "cmp{l} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins GR32:$src1, i32imm:$src2),
+ "cmp{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
def CMP8mi : Ii8 <0x80, MRM7m,
- (ops i8mem :$src1, i8imm :$src2),
- "cmp{b} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins i8mem :$src1, i8imm :$src2),
+ "cmp{b}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (loadi8 addr:$src1), imm:$src2),
+ (implicit EFLAGS)]>;
def CMP16mi : Ii16<0x81, MRM7m,
- (ops i16mem:$src1, i16imm:$src2),
- "cmp{w} {$src2, $src1|$src1, $src2}", []>, OpSize;
+ (outs), (ins i16mem:$src1, i16imm:$src2),
+ "cmp{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (loadi16 addr:$src1), imm:$src2),
+ (implicit EFLAGS)]>, OpSize;
def CMP32mi : Ii32<0x81, MRM7m,
- (ops i32mem:$src1, i32imm:$src2),
- "cmp{l} {$src2, $src1|$src1, $src2}", []>;
+ (outs), (ins i32mem:$src1, i32imm:$src2),
+ "cmp{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (loadi32 addr:$src1), imm:$src2),
+ (implicit EFLAGS)]>;
+def CMP16ri8 : Ii8<0x83, MRM7r,
+ (outs), (ins GR16:$src1, i16i8imm:$src2),
+ "cmp{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR16:$src1, i16immSExt8:$src2),
+ (implicit EFLAGS)]>, OpSize;
+def CMP16mi8 : Ii8<0x83, MRM7m,
+ (outs), (ins i16mem:$src1, i16i8imm:$src2),
+ "cmp{w}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
+ (implicit EFLAGS)]>, OpSize;
+def CMP32mi8 : Ii8<0x83, MRM7m,
+ (outs), (ins i32mem:$src1, i32i8imm:$src2),
+ "cmp{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
+ (implicit EFLAGS)]>;
+def CMP32ri8 : Ii8<0x83, MRM7r,
+ (outs), (ins GR32:$src1, i32i8imm:$src2),
+ "cmp{l}\t{$src2, $src1|$src1, $src2}",
+ [(X86cmp GR32:$src1, i32immSExt8:$src2),
+ (implicit EFLAGS)]>;
+} // Defs = [EFLAGS]
// Sign/Zero extenders
-def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src),
- "movs{bw|x} {$src, $dst|$dst, $src}",
- [(set R16:$dst, (sext R8:$src))]>, TB, OpSize;
-def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src),
- "movs{bw|x} {$src, $dst|$dst, $src}",
- [(set R16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
-def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src),
- "movs{bl|x} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (sext R8:$src))]>, TB;
-def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src),
- "movs{bl|x} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (sextloadi32i8 addr:$src))]>, TB;
-def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src),
- "movs{wl|x} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (sext R16:$src))]>, TB;
-def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src),
- "movs{wl|x} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (sextloadi32i16 addr:$src))]>, TB;
-
-def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src),
- "movz{bw|x} {$src, $dst|$dst, $src}",
- [(set R16:$dst, (zext R8:$src))]>, TB, OpSize;
-def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src),
- "movz{bw|x} {$src, $dst|$dst, $src}",
- [(set R16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
-def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src),
- "movz{bl|x} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (zext R8:$src))]>, TB;
-def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src),
- "movz{bl|x} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (zextloadi32i8 addr:$src))]>, TB;
-def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src),
- "movz{wl|x} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (zext R16:$src))]>, TB;
-def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src),
- "movz{wl|x} {$src, $dst|$dst, $src}",
- [(set R32:$dst, (zextloadi32i16 addr:$src))]>, TB;
-
-// Handling 1 bit zextload and sextload
-def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
-def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
-def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
-def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
+def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
+ "movs{bw|x}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
+def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
+ "movs{bw|x}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
+def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
+ "movs{bl|x}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (sext GR8:$src))]>, TB;
+def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
+ "movs{bl|x}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
+def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
+ "movs{wl|x}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (sext GR16:$src))]>, TB;
+def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
+ "movs{wl|x}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
+
+def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
+ "movz{bw|x}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
+def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
+ "movz{bw|x}\t{$src, $dst|$dst, $src}",
+ [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
+def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
+ "movz{bl|x}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (zext GR8:$src))]>, TB;
+def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
+ "movz{bl|x}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
+def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
+ "movz{wl|x}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (zext GR16:$src))]>, TB;
+def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
+ "movz{wl|x}\t{$src, $dst|$dst, $src}",
+ [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
+
+let Defs = [AX], Uses = [AL] in
+def CBW : I<0x98, RawFrm, (outs), (ins),
+ "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
+let Defs = [EAX], Uses = [AX] in
+def CWDE : I<0x98, RawFrm, (outs), (ins),
+ "{cwtl|cwde}", []>; // EAX = signext(AX)
+
+let Defs = [AX,DX], Uses = [AX] in
+def CWD : I<0x99, RawFrm, (outs), (ins),
+ "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
+let Defs = [EAX,EDX], Uses = [EAX] in
+def CDQ : I<0x99, RawFrm, (outs), (ins),
+ "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
+
//===----------------------------------------------------------------------===//
-// XMM Floating point support (requires SSE2)
+// Alias Instructions
//===----------------------------------------------------------------------===//
-def MOVSSrr : I<0x10, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
- "movss {$src, $dst|$dst, $src}", []>, XS;
-def MOVSSrm : I<0x10, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
- "movss {$src, $dst|$dst, $src}", []>, XS;
-def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, V4F4:$src),
- "movss {$src, $dst|$dst, $src}", []>, XS;
-def MOVSDrr : I<0x10, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
- "movsd {$src, $dst|$dst, $src}", []>, XD;
-def MOVSDrm : I<0x10, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
- "movsd {$src, $dst|$dst, $src}", []>, XD;
-def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, V2F8:$src),
- "movsd {$src, $dst|$dst, $src}", []>, XD;
-
-def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V2F8:$src),
- "cvttsd2si {$src, $dst|$dst, $src}",
- [(set R32:$dst, (fp_to_sint V2F8:$src))]>, XD;
-def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
- "cvttsd2si {$src, $dst|$dst, $src}", []>, XD;
-def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, V4F4:$src),
- "cvttss2si {$src, $dst|$dst, $src}",
- [(set R32:$dst, (fp_to_sint V4F4:$src))]>, XS;
-def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
- "cvttss2si {$src, $dst|$dst, $src}", []>, XS;
-def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops V4F4:$dst, V2F8:$src),
- "cvtsd2ss {$src, $dst|$dst, $src}",
- [(set V4F4:$dst, (fround V2F8:$src))]>, XS;
-def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops V4F4:$dst, f64mem:$src),
- "cvtsd2ss {$src, $dst|$dst, $src}", []>, XS;
-def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops V2F8:$dst, V4F4:$src),
- "cvtss2sd {$src, $dst|$dst, $src}",
- [(set V2F8:$dst, (fextend V4F4:$src))]>, XD;
-def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops V2F8:$dst, f32mem:$src),
- "cvtss2sd {$src, $dst|$dst, $src}", []>, XD;
-def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops V4F4:$dst, R32:$src),
- "cvtsi2ss {$src, $dst|$dst, $src}",
- [(set V4F4:$dst, (sint_to_fp R32:$src))]>, XS;
-def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops V4F4:$dst, i32mem:$src),
- "cvtsi2ss {$src, $dst|$dst, $src}", []>, XS;
-def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops V2F8:$dst, R32:$src),
- "cvtsi2sd {$src, $dst|$dst, $src}",
- [(set V2F8:$dst, (sint_to_fp R32:$src))]>, XD;
-def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops V2F8:$dst, i32mem:$src),
- "cvtsi2sd {$src, $dst|$dst, $src}", []>, XD;
-
-def SQRTSSrm : I<0x51, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
- "sqrtss {$src, $dst|$dst, $src}", []>, XS;
-def SQRTSSrr : I<0x51, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
- "sqrtss {$src, $dst|$dst, $src}",
- [(set V4F4:$dst, (fsqrt V4F4:$src))]>, XS;
-def SQRTSDrm : I<0x51, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
- "sqrtsd {$src, $dst|$dst, $src}", []>, XD;
-def SQRTSDrr : I<0x51, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
- "sqrtsd {$src, $dst|$dst, $src}",
- [(set V2F8:$dst, (fsqrt V2F8:$src))]>, XD;
-
-def UCOMISDrr: I<0x2E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src),
- "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize;
-def UCOMISDrm: I<0x2E, MRMSrcMem, (ops V2F8:$dst, f64mem:$src),
- "ucomisd {$src, $dst|$dst, $src}", []>, TB, OpSize;
-def UCOMISSrr: I<0x2E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src),
- "ucomiss {$src, $dst|$dst, $src}", []>, TB;
-def UCOMISSrm: I<0x2E, MRMSrcMem, (ops V4F4:$dst, f32mem:$src),
- "ucomiss {$src, $dst|$dst, $src}", []>, TB;
-
-// Pseudo-instructions that map fld0 to xorps/xorpd for sse.
+// Alias instructions that map movr0 to xor.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
-def FLD0SS : I<0x57, MRMSrcReg, (ops V4F4:$dst),
- "xorps $dst, $dst", []>, TB;
-def FLD0SD : I<0x57, MRMSrcReg, (ops V2F8:$dst),
- "xorpd $dst, $dst", []>, TB, OpSize;
+let Defs = [EFLAGS], isReMaterializable = 1, neverHasSideEffects = 1 in {
+def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
+ "xor{b}\t$dst, $dst",
+ [(set GR8:$dst, 0)]>;
+def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
+ "xor{w}\t$dst, $dst",
+ [(set GR16:$dst, 0)]>, OpSize;
+def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
+ "xor{l}\t$dst, $dst",
+ [(set GR32:$dst, 0)]>;
+}
-let isTwoAddress = 1 in {
-let isCommutable = 1 in {
-def ADDSSrr : I<0x58, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "addss {$src2, $dst|$dst, $src2}",
- [(set V4F4:$dst, (fadd V4F4:$src1, V4F4:$src2))]>, XS;
-def ADDSDrr : I<0x58, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "addsd {$src2, $dst|$dst, $src2}",
- [(set V2F8:$dst, (fadd V2F8:$src1, V2F8:$src2))]>, XD;
-def ANDPSrr : I<0x54, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "andps {$src2, $dst|$dst, $src2}", []>, TB;
-def ANDPDrr : I<0x54, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "andpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def MULSSrr : I<0x59, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "mulss {$src2, $dst|$dst, $src2}",
- [(set V4F4:$dst, (fmul V4F4:$src1, V4F4:$src2))]>, XS;
-def MULSDrr : I<0x59, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "mulsd {$src2, $dst|$dst, $src2}",
- [(set V2F8:$dst, (fmul V2F8:$src1, V2F8:$src2))]>, XD;
-def ORPSrr : I<0x56, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "orps {$src2, $dst|$dst, $src2}", []>, TB;
-def ORPDrr : I<0x56, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "orpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def XORPSrr : I<0x57, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "xorps {$src2, $dst|$dst, $src2}", []>, TB;
-def XORPDrr : I<0x57, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "xorpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
+// Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
+// those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
+def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
+def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}", []>;
+
+def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
+def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}", []>;
+let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
+def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
+def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}", []>;
}
-def ANDNPSrr : I<0x55, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "andnps {$src2, $dst|$dst, $src2}", []>, TB;
-def ANDNPDrr : I<0x55, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "andnpd {$src2, $dst|$dst, $src2}", []>, TB, OpSize;
-def ADDSSrm : I<0x58, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
- "addss {$src2, $dst|$dst, $src2}", []>, XS;
-def ADDSDrm : I<0x58, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
- "addsd {$src2, $dst|$dst, $src2}", []>, XD;
-def MULSSrm : I<0x59, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
- "mulss {$src2, $dst|$dst, $src2}", []>, XS;
-def MULSDrm : I<0x59, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
- "mulsd {$src2, $dst|$dst, $src2}", []>, XD;
-
-def DIVSSrm : I<0x5E, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
- "divss {$src2, $dst|$dst, $src2}", []>, XS;
-def DIVSSrr : I<0x5E, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "divss {$src2, $dst|$dst, $src2}",
- [(set V4F4:$dst, (fdiv V4F4:$src1, V4F4:$src2))]>, XS;
-def DIVSDrm : I<0x5E, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
- "divsd {$src2, $dst|$dst, $src2}", []>, XD;
-def DIVSDrr : I<0x5E, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "divsd {$src2, $dst|$dst, $src2}",
- [(set V2F8:$dst, (fdiv V2F8:$src1, V2F8:$src2))]>, XD;
-
-def SUBSSrm : I<0x5C, MRMSrcMem, (ops V4F4:$dst, V4F4:$src1, f32mem:$src2),
- "subss {$src2, $dst|$dst, $src2}", []>, XS;
-def SUBSSrr : I<0x5C, MRMSrcReg, (ops V4F4:$dst, V4F4:$src1, V4F4:$src2),
- "subss {$src2, $dst|$dst, $src2}",
- [(set V4F4:$dst, (fsub V4F4:$src1, V4F4:$src2))]>, XS;
-def SUBSDrm : I<0x5C, MRMSrcMem, (ops V2F8:$dst, V2F8:$src1, f64mem:$src2),
- "subsd {$src2, $dst|$dst, $src2}", []>, XD;
-def SUBSDrr : I<0x5C, MRMSrcReg, (ops V2F8:$dst, V2F8:$src1, V2F8:$src2),
- "subsd {$src2, $dst|$dst, $src2}",
- [(set V2F8:$dst, (fsub V2F8:$src1, V2F8:$src2))]>, XD;
-
-def CMPSSrr : I<0xC2, MRMSrcReg,
- (ops V4F4:$dst, V4F4:$src1, V4F4:$src, SSECC:$cc),
- "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS;
-def CMPSSrm : I<0xC2, MRMSrcMem,
- (ops V4F4:$dst, V4F4:$src1, f32mem:$src, SSECC:$cc),
- "cmp${cc}ss {$src, $dst|$dst, $src}", []>, XS;
-def CMPSDrr : I<0xC2, MRMSrcReg,
- (ops V2F8:$dst, V2F8:$src1, V2F8:$src, SSECC:$cc),
- "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD;
-def CMPSDrm : I<0xC2, MRMSrcMem,
- (ops V2F8:$dst, V2F8:$src1, f64mem:$src, SSECC:$cc),
- "cmp${cc}sd {$src, $dst|$dst, $src}", []>, XD;
+def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
+ "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
+def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
+ "mov{l}\t{$src, $dst|$dst, $src}", []>;
+
+//===----------------------------------------------------------------------===//
+// Thread Local Storage Instructions
+//
+
+let Uses = [EBX] in
+def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
+ "leal\t${sym:mem}(,%ebx,1), $dst",
+ [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>;
+
+let AddedComplexity = 10 in
+def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
+ "movl\t%gs:($src), $dst",
+ [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
+
+let AddedComplexity = 15 in
+def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
+ "movl\t%gs:${src:mem}, $dst",
+ [(set GR32:$dst,
+ (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
+
+def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
+ "movl\t%gs:0, $dst",
+ [(set GR32:$dst, X86TLStp)]>;
+
+//===----------------------------------------------------------------------===//
+// DWARF Pseudo Instructions
+//
+
+def DWARF_LOC : I<0, Pseudo, (outs),
+ (ins i32imm:$line, i32imm:$col, i32imm:$file),
+ ".loc\t${file:debug} ${line:debug} ${col:debug}",
+ [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
+ (i32 imm:$file))]>;
+
+//===----------------------------------------------------------------------===//
+// EH Pseudo Instructions
+//
+let isTerminator = 1, isReturn = 1, isBarrier = 1,
+ hasCtrlDep = 1 in {
+def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
+ "ret\t#eh_return, addr: $addr",
+ [(X86ehret GR32:$addr)]>;
+
}
//===----------------------------------------------------------------------===//
-// Miscellaneous Instructions
+// Non-Instruction Patterns
//===----------------------------------------------------------------------===//
-def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", []>, TB, Imp<[],[EAX,EDX]>;
+// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
+def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
+def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
+def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
+def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
+def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
+
+def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
+ (ADD32ri GR32:$src1, tconstpool:$src2)>;
+def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
+ (ADD32ri GR32:$src1, tjumptable:$src2)>;
+def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
+ (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
+def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
+ (ADD32ri GR32:$src1, texternalsym:$src2)>;
+
+def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
+ (MOV32mi addr:$dst, tglobaladdr:$src)>;
+def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
+ (MOV32mi addr:$dst, texternalsym:$src)>;
+
+// Calls
+// tailcall stuff
+def : Pat<(X86tailcall GR32:$dst),
+ (TAILCALL)>;
+
+def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
+ (TAILCALL)>;
+def : Pat<(X86tailcall (i32 texternalsym:$dst)),
+ (TAILCALL)>;
+
+def : Pat<(X86tcret GR32:$dst, imm:$off),
+ (TCRETURNri GR32:$dst, imm:$off)>;
+
+def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
+ (TCRETURNdi texternalsym:$dst, imm:$off)>;
+
+def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
+ (TCRETURNdi texternalsym:$dst, imm:$off)>;
+
+def : Pat<(X86call (i32 tglobaladdr:$dst)),
+ (CALLpcrel32 tglobaladdr:$dst)>;
+def : Pat<(X86call (i32 texternalsym:$dst)),
+ (CALLpcrel32 texternalsym:$dst)>;
+
+// X86 specific add which produces a flag.
+def : Pat<(addc GR32:$src1, GR32:$src2),
+ (ADD32rr GR32:$src1, GR32:$src2)>;
+def : Pat<(addc GR32:$src1, (load addr:$src2)),
+ (ADD32rm GR32:$src1, addr:$src2)>;
+def : Pat<(addc GR32:$src1, imm:$src2),
+ (ADD32ri GR32:$src1, imm:$src2)>;
+def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
+ (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
+
+def : Pat<(subc GR32:$src1, GR32:$src2),
+ (SUB32rr GR32:$src1, GR32:$src2)>;
+def : Pat<(subc GR32:$src1, (load addr:$src2)),
+ (SUB32rm GR32:$src1, addr:$src2)>;
+def : Pat<(subc GR32:$src1, imm:$src2),
+ (SUB32ri GR32:$src1, imm:$src2)>;
+def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
+ (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
+
+def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
+ (MOV8mi addr:$dst, imm:$src)>;
+def : Pat<(truncstorei1 GR8:$src, addr:$dst),
+ (MOV8mr addr:$dst, GR8:$src)>;
+
+// Comparisons.
+
+// TEST R,R is smaller than CMP R,0
+def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+ (TEST8rr GR8:$src1, GR8:$src1)>;
+def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
+ (TEST16rr GR16:$src1, GR16:$src1)>;
+def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
+ (TEST32rr GR32:$src1, GR32:$src1)>;
+
+// {s|z}extload bool -> {s|z}extload byte
+def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
+def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
+def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
+def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
+def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
+
+// extload bool -> extload byte
+def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
+def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
+def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
+def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
+def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
+def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
+
+// anyext -> zext
+def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
+def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
+def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
+def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
+def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
+def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
+
+// (and (i32 load), 255) -> (zextload i8)
+def : Pat<(i32 (and (loadi32 addr:$src), (i32 255))), (MOVZX32rm8 addr:$src)>;
+def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>;
+
+//===----------------------------------------------------------------------===//
+// Some peepholes
+//===----------------------------------------------------------------------===//
+
+// (shl x, 1) ==> (add x, x)
+def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
+def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
+def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
+
+// (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
+def : Pat<(or (srl GR32:$src1, CL:$amt),
+ (shl GR32:$src2, (sub 32, CL:$amt))),
+ (SHRD32rrCL GR32:$src1, GR32:$src2)>;
+
+def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
+ (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
+ (SHRD32mrCL addr:$dst, GR32:$src2)>;
+
+// (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
+def : Pat<(or (shl GR32:$src1, CL:$amt),
+ (srl GR32:$src2, (sub 32, CL:$amt))),
+ (SHLD32rrCL GR32:$src1, GR32:$src2)>;
+
+def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
+ (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
+ (SHLD32mrCL addr:$dst, GR32:$src2)>;
+
+// (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
+def : Pat<(or (srl GR16:$src1, CL:$amt),
+ (shl GR16:$src2, (sub 16, CL:$amt))),
+ (SHRD16rrCL GR16:$src1, GR16:$src2)>;
+
+def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
+ (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
+ (SHRD16mrCL addr:$dst, GR16:$src2)>;
+
+// (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
+def : Pat<(or (shl GR16:$src1, CL:$amt),
+ (srl GR16:$src2, (sub 16, CL:$amt))),
+ (SHLD16rrCL GR16:$src1, GR16:$src2)>;
+
+def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
+ (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
+ (SHLD16mrCL addr:$dst, GR16:$src2)>;
//===----------------------------------------------------------------------===//
-// Stack-based Floating point support
+// Floating Point Stack Support
//===----------------------------------------------------------------------===//
-// FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
+include "X86InstrFPStack.td"
-// Floating point instruction template
-class FPI<bits<8> o, Format F, FPFormat fp, dag ops, string asm>
- : X86Inst<o, F, NoImm, ops, asm> {
- let FPForm = fp; let FPFormBits = FPForm.Value;
-}
+//===----------------------------------------------------------------------===//
+// X86-64 Support
+//===----------------------------------------------------------------------===//
-// Pseudo instructions for floating point. We use these pseudo instructions
-// because they can be expanded by the fp spackifier into one of many different
-// forms of instructions for doing these operations. Until the stackifier runs,
-// we prefer to be abstract.
-def FpMOV : FPI<0, Pseudo, SpecialFP,
- (ops RFP:$dst, RFP:$src), "">; // f1 = fmov f2
-def FpADD : FPI<0, Pseudo, TwoArgFP ,
- (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fadd f2, f3
-def FpSUB : FPI<0, Pseudo, TwoArgFP ,
- (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fsub f2, f3
-def FpMUL : FPI<0, Pseudo, TwoArgFP ,
- (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fmul f2, f3
-def FpDIV : FPI<0, Pseudo, TwoArgFP ,
- (ops RFP:$dst, RFP:$src1, RFP:$src2), "">; // f1 = fdiv f2, f3
-
-def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$dst), "">,
- Imp<[ST0], []>; // FPR = ST(0)
-
-def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP:$src), "">,
- Imp<[], [ST0]>; // ST(0) = FPR
-
-// FADD reg, mem: Before stackification, these are represented by:
-// R1 = FADD* R2, [mem]
-def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real]
- (ops f32mem:$src, variable_ops),
- "fadd{s} $src">;
-def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real]
- (ops f64mem:$src, variable_ops),
- "fadd{l} $src">;
-//def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
-//def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
-
-// FMUL reg, mem: Before stackification, these are represented by:
-// R1 = FMUL* R2, [mem]
-def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real]
- (ops f32mem:$src, variable_ops),
- "fmul{s} $src">;
-def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real]
- (ops f64mem:$src, variable_ops),
- "fmul{l} $src">;
-// ST(0) = ST(0) * [mem16int]
-//def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>;
-// ST(0) = ST(0) * [mem32int]
-//def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>;
-
-// FSUB reg, mem: Before stackification, these are represented by:
-// R1 = FSUB* R2, [mem]
-def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real]
- (ops f32mem:$src, variable_ops),
- "fsub{s} $src">;
-def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real]
- (ops f64mem:$src, variable_ops),
- "fsub{l} $src">;
-// ST(0) = ST(0) - [mem16int]
-//def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>;
-// ST(0) = ST(0) - [mem32int]
-//def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>;
-
-// FSUBR reg, mem: Before stackification, these are represented by:
-// R1 = FSUBR* R2, [mem]
-
-// Note that the order of operands does not reflect the operation being
-// performed.
-def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0)
- (ops f32mem:$src, variable_ops),
- "fsubr{s} $src">;
-def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0)
- (ops f64mem:$src, variable_ops),
- "fsubr{l} $src">;
-// ST(0) = [mem16int] - ST(0)
-//def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>;
-// ST(0) = [mem32int] - ST(0)
-//def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>;
-
-// FDIV reg, mem: Before stackification, these are represented by:
-// R1 = FDIV* R2, [mem]
-def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real]
- (ops f32mem:$src, variable_ops),
- "fdiv{s} $src">;
-def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real]
- (ops f64mem:$src, variable_ops),
- "fdiv{l} $src">;
-// ST(0) = ST(0) / [mem16int]
-//def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>;
-// ST(0) = ST(0) / [mem32int]
-//def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>;
-
-// FDIVR reg, mem: Before stackification, these are represented by:
-// R1 = FDIVR* R2, [mem]
-// Note that the order of operands does not reflect the operation being
-// performed.
-def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0)
- (ops f32mem:$src, variable_ops),
- "fdivr{s} $src">;
-def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0)
- (ops f64mem:$src, variable_ops),
- "fdivr{l} $src">;
-// ST(0) = [mem16int] / ST(0)
-//def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>;
-// ST(0) = [mem32int] / ST(0)
-//def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>;
-
-
-// Floating point cmovs...
-let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
- def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA;
- def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA;
- def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
- def FCMOVP : FPI<0xD8, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA;
- def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB;
- def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmova {$op, %ST(0)|%ST(0), $op}">, DB;
- def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
- def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP,
- (ops RST:$op, variable_ops),
- "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB;
-}
+include "X86InstrX86-64.td"
-// Floating point loads & stores...
-// FIXME: these are all marked variable_ops because they have an implicit
-// destination. Instructions like FILD* that are generated by the instruction
-// selector (not the fp stackifier) need more accurate operand accounting.
-def FLDrr : FPI<0xC0, AddRegFrm, NotFP,
- (ops RST:$src, variable_ops),
- "fld $src">, D9;
-def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP,
- (ops f32mem:$src, variable_ops),
- "fld{s} $src">;
-def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP,
- (ops f64mem:$src, variable_ops),
- "fld{l} $src">;
-def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP,
- (ops f80mem:$src, variable_ops),
- "fld{t} $src">;
-def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP,
- (ops i16mem:$src, variable_ops),
- "fild{s} $src">;
-def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP,
- (ops i32mem:$src, variable_ops),
- "fild{l} $src">;
-def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP,
- (ops i64mem:$src, variable_ops),
- "fild{ll} $src">;
-
-def FSTrr : FPI<0xD0, AddRegFrm, NotFP,
- (ops RST:$op, variable_ops),
- "fst $op">, DD;
-def FSTPrr : FPI<0xD8, AddRegFrm, NotFP,
- (ops RST:$op, variable_ops),
- "fstp $op">, DD;
-def FST32m : FPI<0xD9, MRM2m, OneArgFP,
- (ops f32mem:$op, variable_ops),
- "fst{s} $op">;
-def FST64m : FPI<0xDD, MRM2m, OneArgFP,
- (ops f64mem:$op, variable_ops),
- "fst{l} $op">;
-def FSTP32m : FPI<0xD9, MRM3m, OneArgFP,
- (ops f32mem:$op, variable_ops),
- "fstp{s} $op">;
-def FSTP64m : FPI<0xDD, MRM3m, OneArgFP,
- (ops f64mem:$op, variable_ops),
- "fstp{l} $op">;
-def FSTP80m : FPI<0xDB, MRM7m, OneArgFP,
- (ops f80mem:$op, variable_ops),
- "fstp{t} $op">;
-
-def FIST16m : FPI<0xDF, MRM2m , OneArgFP,
- (ops i16mem:$op, variable_ops),
- "fist{s} $op">;
-def FIST32m : FPI<0xDB, MRM2m , OneArgFP,
- (ops i32mem:$op, variable_ops),
- "fist{l} $op">;
-def FISTP16m : FPI<0xDF, MRM3m , NotFP ,
- (ops i16mem:$op, variable_ops),
- "fistp{s} $op">;
-def FISTP32m : FPI<0xDB, MRM3m , NotFP ,
- (ops i32mem:$op, variable_ops),
- "fistp{l} $op">;
-def FISTP64m : FPI<0xDF, MRM7m , OneArgFP,
- (ops i64mem:$op, variable_ops),
- "fistp{ll} $op">;
-
-def FXCH : FPI<0xC8, AddRegFrm, NotFP,
- (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
-
-// Floating point constant loads...
-def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops variable_ops), "fldz">, D9;
-def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops variable_ops), "fld1">, D9;
-
-
-// Unary operations...
-def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, // f1 = fchs f2
- (ops variable_ops),
- "fchs">, D9;
-def FABS : FPI<0xE1, RawFrm, OneArgFPRW, // f1 = fabs f2
- (ops variable_ops),
- "fabs">, D9;
-def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW, // fsqrt ST(0)
- (ops variable_ops),
- "fsqrt">, D9;
-def FSIN : FPI<0xFE, RawFrm, OneArgFPRW, // fsin ST(0)
- (ops variable_ops),
- "fsin">, D9;
-def FCOS : FPI<0xFF, RawFrm, OneArgFPRW, // fcos ST(0)
- (ops variable_ops),
- "fcos">, D9;
-def FTST : FPI<0xE4, RawFrm, OneArgFP , // ftst ST(0)
- (ops variable_ops),
- "ftst">, D9;
-
-// Binary arithmetic operations...
-class FPST0rInst<bits<8> o, dag ops, string asm>
- : I<o, AddRegFrm, ops, asm, []>, D8 {
- list<Register> Uses = [ST0];
- list<Register> Defs = [ST0];
-}
-class FPrST0Inst<bits<8> o, dag ops, string asm>
- : I<o, AddRegFrm, ops, asm, []>, DC {
- list<Register> Uses = [ST0];
-}
-class FPrST0PInst<bits<8> o, dag ops, string asm>
- : I<o, AddRegFrm, ops, asm, []>, DE {
- list<Register> Uses = [ST0];
-}
+//===----------------------------------------------------------------------===//
+// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
+//===----------------------------------------------------------------------===//
+
+include "X86InstrMMX.td"
+
+//===----------------------------------------------------------------------===//
+// XMM Floating point support (requires SSE / SSE2)
+//===----------------------------------------------------------------------===//
-def FADDST0r : FPST0rInst <0xC0, (ops RST:$op),
- "fadd $op">;
-def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op),
- "fadd {%ST(0), $op|$op, %ST(0)}">;
-def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op),
- "faddp $op">;
-
-// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
-// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
-// we have to put some 'r's in and take them out of weird places.
-def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op),
- "fsubr $op">;
-def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op),
- "fsub{r} {%ST(0), $op|$op, %ST(0)}">;
-def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op),
- "fsub{r}p $op">;
-
-def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op),
- "fsub $op">;
-def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op),
- "fsub{|r} {%ST(0), $op|$op, %ST(0)}">;
-def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op),
- "fsub{|r}p $op">;
-
-def FMULST0r : FPST0rInst <0xC8, (ops RST:$op),
- "fmul $op">;
-def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op),
- "fmul {%ST(0), $op|$op, %ST(0)}">;
-def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op),
- "fmulp $op">;
-
-def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op),
- "fdivr $op">;
-def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op),
- "fdiv{r} {%ST(0), $op|$op, %ST(0)}">;
-def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op),
- "fdiv{r}p $op">;
-
-def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i)
- "fdiv $op">;
-def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i)
- "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">;
-def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop
- "fdiv{|r}p $op">;
-
-// Floating point compares
-def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i)
- (ops RST:$reg, variable_ops),
- "fucom $reg">, DD, Imp<[ST0],[]>;
-def FUCOMPr : I<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
- (ops RST:$reg, variable_ops),
- "fucomp $reg", []>, DD, Imp<[ST0],[]>;
-def FUCOMPPr : I<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
- (ops variable_ops),
- "fucompp", []>, DA, Imp<[ST0],[]>;
-
-def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i)
- (ops RST:$reg, variable_ops),
- "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
-def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
- (ops RST:$reg, variable_ops),
- "fucomip {$reg, %ST(0)|%ST(0), $reg}", []>, DF, Imp<[ST0],[]>;
-
-
-// Floating point flag ops
-def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
- (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
-
-def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
- (ops i16mem:$dst), "fnstcw $dst", []>;
-def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
- (ops i16mem:$dst), "fldcw $dst", []>;
+include "X86InstrSSE.td"
projects / oota-llvm.git / blobdiff