Emit more efficient 64-bit operations when the RHS is a constant, and one

[oota-llvm.git] / lib / Target / X86 / X86InstrInfo.cpp

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index e54883395d2d76e0f1a7b525cf4824b6cca272a7..f93409361ba8cef942d786de1358d5e5cf2d38bd 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1,27 +1,40 @@
-//===- X86InstrInfo.cpp - X86 Instruction Information ---------------===//
+//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
 //
-// This file contains the X86 implementation of the MachineInstrInfo class.
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This file contains the X86 implementation of the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86InstrInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include <iostream>
-
-// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
-// descriptors
-//
-static const MachineInstrDescriptor X86Insts[] = {
-#define I(ENUM, NAME, FLAGS, TSFLAGS)   \
-             { NAME,                    \
-               -1, /* Always vararg */  \
-               ((TSFLAGS) & X86II::Void) ? -1 : 0,  /* Result is in 0 */ \
-               0, false, 0, 0, TSFLAGS, FLAGS, TSFLAGS },
-#include "X86InstrInfo.def"
-};
+#include "X86.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "X86GenInstrInfo.inc"
+using namespace llvm;
 
 X86InstrInfo::X86InstrInfo()
-  : MachineInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
+  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
 }
 
 
+bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
+                               unsigned& sourceReg,
+                               unsigned& destReg) const {
+  MachineOpCode oc = MI.getOpcode();
+  if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
+      oc == X86::FpMOV) {
+      assert(MI.getNumOperands() == 2 &&
+             MI.getOperand(0).isRegister() &&
+             MI.getOperand(1).isRegister() &&
+             "invalid register-register move instruction");
+      sourceReg = MI.getOperand(1).getReg();
+      destReg = MI.getOperand(0).getReg();
+      return true;
+  }
+  return false;
+}