Rename ConstantSDNode::getValue to getZExtValue, for consistency

[oota-llvm.git] / lib / Target / X86 / X86Instr64bit.td

diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 239ae972302f88d508e4c69578ea4f02e06f7ec0..88a8c0803fa0e700f3f013b7a92f999369b0eda2 100644 (file)
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -46,25 +46,25 @@ def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
 def i64immSExt32  : PatLeaf<(i64 imm), [{
   // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
   // sign extended field.
-  return (int64_t)N->getValue() == (int32_t)N->getValue();
+  return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
 }]>;
 
 def i64immZExt32  : PatLeaf<(i64 imm), [{
   // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
   // unsignedsign extended field.
-  return (uint64_t)N->getValue() == (uint32_t)N->getValue();
+  return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
 }]>;
 
 def i64immSExt8  : PatLeaf<(i64 imm), [{
   // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
   // sign extended field.
-  return (int64_t)N->getValue() == (int8_t)N->getValue();
+  return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
 }]>;
 
 def i64immFFFFFFFF  : PatLeaf<(i64 imm), [{
   // i64immFFFFFFFF - True if this is a specific constant we can't write in
   // tblgen files.
-  return N->getValue() == 0x00000000FFFFFFFFULL;
+  return N->getZExtValue() == 0x00000000FFFFFFFFULL;
 }]>;
 
 
@@ -129,6 +129,17 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
                      [(brind (loadi64 addr:$dst))]>;
 }
 
+//===----------------------------------------------------------------------===//
+// EH Pseudo Instructions
+//
+let isTerminator = 1, isReturn = 1, isBarrier = 1,
+    hasCtrlDep = 1 in {
+def EH_RETURN64   : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
+                     "ret\t#eh_return, addr: $addr",
+                     [(X86ehret GR64:$addr)]>;
+
+}
+
 //===----------------------------------------------------------------------===//
 //  Miscellaneous Instructions...
 //
@@ -767,7 +778,7 @@ def OR64mi8  : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
                   [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
 
 let isTwoAddress = 1 in {
-let isCommutable = 1, isAsCheapAsAMove = 1 in
+let isCommutable = 1 in
 def XOR64rr  : RI<0x31, MRMDestReg,  (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 
                   "xor{q}\t{$src2, $dst|$dst, $src2}",
                   [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
@@ -1341,6 +1352,22 @@ def : Pat<(i8 (trunc GR16:$src)),
 // (shl x, 1) ==> (add x, x)
 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
 
+// (shl x (and y, 63)) ==> (shl x, y)
+def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
+          (SHL64rCL GR64:$src1)>;
+def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
+          (SHL64mCL addr:$dst)>;
+
+def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
+          (SHR64rCL GR64:$src1)>;
+def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
+          (SHR64mCL addr:$dst)>;
+
+def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
+          (SAR64rCL GR64:$src1)>;
+def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
+          (SAR64mCL addr:$dst)>;
+
 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
 def : Pat<(or (srl GR64:$src1, CL:$amt),
               (shl GR64:$src2, (sub 64, CL:$amt))),