F = &MachineFunction::construct(&Fn, TM);
visit(Fn);
RegMap.clear();
+ CurReg = MRegisterInfo::FirstVirtualRegister;
F = 0;
return false; // We never modify the LLVM itself.
}
// Visitation methods for various instructions. These methods simply emit
// fixed X86 code for each instruction.
//
+
+ // Control flow operators
void visitReturnInst(ReturnInst &RI);
void visitBranchInst(BranchInst &BI);
+ void visitCallInst(CallInst &I);
// Arithmetic operators
void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
// Other operators
void visitShiftInst(ShiftInst &I);
void visitPHINode(PHINode &I);
+ void visitCastInst(CastInst &I);
void visitInstruction(Instruction &I) {
std::cerr << "Cannot instruction select: " << I;
abort();
}
+ void promote32 (const unsigned targetReg, Value *v);
/// copyConstantToRegister - Output the instructions required to put the
/// specified constant into the specified register.
// If this operand is a constant, emit the code to copy the constant into
// the register here...
//
- if (Constant *C = dyn_cast<Constant>(V))
+ if (Constant *C = dyn_cast<Constant>(V)) {
copyConstantToRegister(C, Reg);
+ } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
+ // Move the address of the global into the register
+ BuildMI(BB, X86::MOVir32, 1, Reg).addReg(GV);
+ } else if (Argument *A = dyn_cast<Argument>(V)) {
+ std::cerr << "ERROR: Arguments not implemented in SimpleInstSel\n";
+ } else {
+ assert(0 && "Don't know how to handle a value of this type!");
+ }
return Reg;
}
// FIXME: assuming var1, var2 are in memory, if not, spill to
// stack first
case cFloat: // Floats
- BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
- BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
+ BuildMI (BB, X86::FLDr4, 1).addReg (reg1);
+ BuildMI (BB, X86::FLDr4, 1).addReg (reg2);
break;
case cDouble: // Doubles
- BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
- BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
+ BuildMI (BB, X86::FLDr8, 1).addReg (reg1);
+ BuildMI (BB, X86::FLDr8, 1).addReg (reg2);
break;
case cLong:
default:
BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
}
+/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
+/// operand, in the specified target register.
+void
+ISel::promote32 (const unsigned targetReg, Value *v)
+{
+ unsigned vReg = getReg (v);
+ unsigned Class = getClass (v->getType ());
+ bool isUnsigned = v->getType ()->isUnsigned ();
+ assert (((Class == cByte) || (Class == cShort) || (Class == cInt))
+ && "Unpromotable operand class in promote32");
+ switch (Class)
+ {
+ case cByte:
+ // Extend value into target register (8->32)
+ if (isUnsigned)
+ BuildMI (BB, X86::MOVZXr32r8, 1, targetReg).addReg (vReg);
+ else
+ BuildMI (BB, X86::MOVSXr32r8, 1, targetReg).addReg (vReg);
+ break;
+ case cShort:
+ // Extend value into target register (16->32)
+ if (isUnsigned)
+ BuildMI (BB, X86::MOVZXr32r16, 1, targetReg).addReg (vReg);
+ else
+ BuildMI (BB, X86::MOVSXr32r16, 1, targetReg).addReg (vReg);
+ break;
+ case cInt:
+ // Move value into target register (32->32)
+ BuildMI (BB, X86::MOVrr32, 1, targetReg).addReg (vReg);
+ break;
+ }
+}
/// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
/// we have the following possibilities:
/// ret long, ulong : Move value into EAX/EDX and return
/// ret float/double : Top of FP stack
///
-void ISel::visitReturnInst (ReturnInst &I) {
- if (I.getNumOperands() == 0) {
- // Emit a 'ret' instruction
- BuildMI(BB, X86::RET, 0);
- return;
- }
-
- unsigned val = getReg(I.getOperand(0));
- unsigned Class = getClass(I.getOperand(0)->getType());
- bool isUnsigned = I.getOperand(0)->getType()->isUnsigned();
- switch (Class) {
- case cByte:
- // ret sbyte, ubyte: Extend value into EAX and return
- if (isUnsigned)
- BuildMI (BB, X86::MOVZXr32r8, 1, X86::EAX).addReg (val);
- else
- BuildMI (BB, X86::MOVSXr32r8, 1, X86::EAX).addReg (val);
- break;
- case cShort:
- // ret short, ushort: Extend value into EAX and return
- if (isUnsigned)
- BuildMI (BB, X86::MOVZXr32r16, 1, X86::EAX).addReg (val);
- else
- BuildMI (BB, X86::MOVSXr32r16, 1, X86::EAX).addReg (val);
- break;
- case cInt:
- // ret int, uint, ptr: Move value into EAX and return
- // MOV EAX, <val>
- BuildMI(BB, X86::MOVrr32, 1, X86::EAX).addReg(val);
- break;
-
- // ret float/double: top of FP stack
- // FLD <val>
- case cFloat: // Floats
- BuildMI(BB, X86::FLDr4, 1).addReg(val);
- break;
- case cDouble: // Doubles
- BuildMI(BB, X86::FLDr8, 1).addReg(val);
- break;
- case cLong:
- // ret long: use EAX(least significant 32 bits)/EDX (most
- // significant 32)...uh, I think so Brain, but how do i call
- // up the two parts of the value from inside this mouse
- // cage? *zort*
- default:
- visitInstruction(I);
- }
-
+void
+ISel::visitReturnInst (ReturnInst &I)
+{
+ if (I.getNumOperands () == 0)
+ {
+ // Emit a 'ret' instruction
+ BuildMI (BB, X86::RET, 0);
+ return;
+ }
+ Value *rv = I.getOperand (0);
+ unsigned Class = getClass (rv->getType ());
+ switch (Class)
+ {
+ // integral return values: extend or move into EAX and return.
+ case cByte:
+ case cShort:
+ case cInt:
+ promote32 (X86::EAX, rv);
+ break;
+ // ret float/double: top of FP stack
+ // FLD <val>
+ case cFloat: // Floats
+ BuildMI (BB, X86::FLDr4, 1).addReg (getReg (rv));
+ break;
+ case cDouble: // Doubles
+ BuildMI (BB, X86::FLDr8, 1).addReg (getReg (rv));
+ break;
+ case cLong:
+ // ret long: use EAX(least significant 32 bits)/EDX (most
+ // significant 32)...uh, I think so Brain, but how do i call
+ // up the two parts of the value from inside this mouse
+ // cage? *zort*
+ default:
+ visitInstruction (I);
+ }
// Emit a 'ret' instruction
- BuildMI(BB, X86::RET, 0);
+ BuildMI (BB, X86::RET, 0);
}
/// visitBranchInst - Handle conditional and unconditional branches here. Note
}
}
+/// visitCallInst - Push args on stack and do a procedure call instruction.
+void
+ISel::visitCallInst (CallInst & CI)
+{
+ // Push the arguments on the stack in reverse order, as specified by
+ // the ABI.
+ for (unsigned i = CI.getNumOperands()-1; i >= 1; --i)
+ {
+ Value *v = CI.getOperand (i);
+ switch (getClass (v->getType ()))
+ {
+ case cByte:
+ case cShort:
+ // Promote V to 32 bits wide, and move the result into EAX,
+ // then push EAX.
+ promote32 (X86::EAX, v);
+ BuildMI (BB, X86::PUSHr32, 1).addReg (X86::EAX);
+ break;
+ case cInt:
+ case cFloat: {
+ unsigned Reg = getReg(v);
+ BuildMI (BB, X86::PUSHr32, 1).addReg(Reg);
+ break;
+ }
+ default:
+ // FIXME: long/ulong/double args not handled.
+ visitInstruction (CI);
+ break;
+ }
+ }
+ // Emit a CALL instruction with PC-relative displacement.
+ BuildMI (BB, X86::CALLpcrel32, 1).addPCDisp (CI.getCalledValue ());
+}
/// visitSimpleBinary - Implement simple binary operators for integral types...
/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or,
visitInstruction(I);
static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
- static const unsigned Clobbers[] ={ X86::AH , X86::DX , X86::EDX };
static const unsigned MulOpcode[]={ X86::MULrr8, X86::MULrr16, X86::MULrr32 };
static const unsigned MovOpcode[]={ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32 };
unsigned Reg = Regs[Class];
- unsigned Clobber = Clobbers[Class];
unsigned Op0Reg = getReg(I.getOperand(0));
unsigned Op1Reg = getReg(I.getOperand(1));
BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
// Emit the appropriate multiply instruction...
- BuildMI(BB, MulOpcode[Class], 3)
- .addReg(Reg, UseAndDef).addReg(Op1Reg).addClobber(Clobber);
+ BuildMI(BB, MulOpcode[Class], 1).addReg(Op1Reg);
// Put the result into the destination register...
BuildMI(BB, MovOpcode[Class], 1, getReg(I)).addReg(Reg);
if (isSigned) {
// Emit a sign extension instruction...
- BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg);
+ BuildMI(BB, ExtOpcode[Class], 0);
} else {
// If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);
}
// Emit the appropriate divide or remainder instruction...
- BuildMI(BB, DivOpcode[isSigned][Class], 2)
- .addReg(Reg, UseAndDef).addReg(ExtReg, UseAndDef).addReg(Op1Reg);
+ BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg);
// Figure out which register we want to pick the result out of...
unsigned DestReg = (I.getOpcode() == Instruction::Div) ? Reg : ExtReg;
const unsigned *OpTab = // Figure out the operand table to use
NonConstantOperand[isLeftShift*2+isOperandSigned];
- BuildMI(BB, OpTab[OperandClass], 2, DestReg).addReg(Op0r).addReg(X86::CL);
+ BuildMI(BB, OpTab[OperandClass], 1, DestReg).addReg(Op0r);
}
}
}
}
+/// visitCastInst - Here we have various kinds of copying with or without
+/// sign extension going on.
+void
+ISel::visitCastInst (CastInst &CI)
+{
+//> cast larger int to smaller int --> copy least significant byte/word w/ mov?
+//
+//I'm not really sure what to do with this. We could insert a pseudo-op
+//that says take the low X bits of a Y bit register, but for now we can just
+//force the value into, say, EAX, then rip out AL or AX. The advantage of
+//the former is that the register allocator could use any register it wants,
+//but for now this obviously doesn't matter. :)
+
+ const Type *targetType = CI.getType ();
+ Value *operand = CI.getOperand (0);
+ unsigned int operandReg = getReg (operand);
+ const Type *sourceType = operand->getType ();
+ unsigned int destReg = getReg (CI);
+
+ // cast to bool:
+ if (targetType == Type::BoolTy) {
+ // Emit Compare
+ BuildMI (BB, X86::CMPri8, 2).addReg (operandReg).addZImm (0);
+ // Emit Set-if-not-zero
+ BuildMI (BB, X86::SETNEr, 1, destReg);
+ return;
+ }
+
+// if size of target type == size of source type
+// Emit Mov reg(target) <- reg(source)
+
+// if size of target type > size of source type
+// if both types are integer types
+// if source type is signed
+// sbyte to short, ushort: Emit movsx 8->16
+// sbyte to int, uint: Emit movsx 8->32
+// short to int, uint: Emit movsx 16->32
+// else if source type is unsigned
+// ubyte to short, ushort: Emit movzx 8->16
+// ubyte to int, uint: Emit movzx 8->32
+// ushort to int, uint: Emit movzx 16->32
+// if both types are fp types
+// float to double: Emit fstp, fld (???)
+
+ visitInstruction (CI);
+}
/// createSimpleX86InstructionSelector - This pass converts an LLVM function
/// into a machine code representation is a very simple peep-hole fashion. The
projects / oota-llvm.git / blobdiff