64-bit (MMX) vectors do not need restrictive alignment.

[oota-llvm.git] / lib / Target / X86 / X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 7ff4e556fcf2954cca24651dfe001ce5c51dd363..e4454709ae87a32162665ad9e65df9927e8a5ff1 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -704,9 +704,6 @@ static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
   if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
     if (VTy->getBitWidth() == 128)
       MaxAlign = 16;
-    else if (VTy->getBitWidth() == 64)
-      if (MaxAlign < 8)
-        MaxAlign = 8;
   } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
     unsigned EltAlign = 0;
     getMaxByValAlign(ATy->getElementType(), EltAlign);
@@ -727,13 +724,14 @@ static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
 
 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
 /// function arguments in the caller parameter area. For X86, aggregates
-/// that contains are placed at 16-byte boundaries while the rest are at
-/// 4-byte boundaries.
+/// that contain SSE vectors are placed at 16-byte boundaries while the rest
+/// are at 4-byte boundaries.
 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
   if (Subtarget->is64Bit())
     return getTargetData()->getABITypeAlignment(Ty);
   unsigned Align = 4;
-  getMaxByValAlign(Ty, Align);
+  if (Subtarget->hasSSE1())
+    getMaxByValAlign(Ty, Align);
   return Align;
 }
 
@@ -4948,9 +4946,9 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
     const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
 
     const unsigned char N86R10 =
-      ((X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10);
+      ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10);
     const unsigned char N86R11 =
-      ((X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11);
+      ((const X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11);
 
     const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
 
@@ -5038,7 +5036,7 @@ SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
 
     const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
     const unsigned char N86Reg =
-      ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
+      ((const X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
     OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
                                 Trmp, TrmpAddr, 0);