//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#define DEBUG_TYPE "x86-emitter"
#include "X86InstrInfo.h"
+#include "X86JITInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "X86Relocations.h"
#include "llvm/CodeGen/MachineCodeEmitter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/Function.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Compiler.h"
+#include "llvm/Support/Debug.h"
#include "llvm/Target/TargetOptions.h"
using namespace llvm;
class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
const X86InstrInfo *II;
const TargetData *TD;
- TargetMachine &TM;
+ X86TargetMachine &TM;
MachineCodeEmitter &MCE;
+ intptr_t PICBaseOffset;
bool Is64BitMode;
+ bool IsPIC;
public:
static char ID;
- explicit Emitter(TargetMachine &tm, MachineCodeEmitter &mce)
+ explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
: MachineFunctionPass((intptr_t)&ID), II(0), TD(0), TM(tm),
- MCE(mce), Is64BitMode(false) {}
- Emitter(TargetMachine &tm, MachineCodeEmitter &mce,
+ MCE(mce), PICBaseOffset(0), Is64BitMode(false),
+ IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
+ Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
const X86InstrInfo &ii, const TargetData &td, bool is64)
: MachineFunctionPass((intptr_t)&ID), II(&ii), TD(&td), TM(tm),
- MCE(mce), Is64BitMode(is64) {}
+ MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
+ IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
bool runOnMachineFunction(MachineFunction &MF);
return "X86 Machine Code Emitter";
}
- void emitInstruction(const MachineInstr &MI);
+ void emitInstruction(const MachineInstr &MI,
+ const TargetInstrDesc *Desc);
+
+ void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<MachineModuleInfo>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
private:
void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
- void emitPCRelativeValue(intptr_t Address);
- void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
- void emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
- int Disp = 0, unsigned PCAdj = 0);
+ void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+ int Disp = 0, intptr_t PCAdj = 0,
+ bool NeedStub = false, bool IsLazy = false);
void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
- unsigned PCAdj = 0);
- void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0);
+ intptr_t PCAdj = 0);
+ void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
+ intptr_t PCAdj = 0);
void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
- unsigned PCAdj = 0);
+ intptr_t PCAdj = 0);
void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
void emitMemModRMByte(const MachineInstr &MI,
unsigned Op, unsigned RegOpcodeField,
- unsigned PCAdj = 0);
+ intptr_t PCAdj = 0);
+
+ unsigned getX86RegNum(unsigned RegNo) const;
- unsigned getX86RegNum(unsigned RegNo);
- bool isX86_64ExtendedReg(const MachineOperand &MO);
- unsigned determineREX(const MachineInstr &MI);
+ bool gvNeedsLazyPtr(const GlobalValue *GV);
};
char Emitter::ID = 0;
}
assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
MF.getTarget().getRelocationModel() != Reloc::Static) &&
"JIT relocation model must be set to static or default!");
- II = ((X86TargetMachine&)MF.getTarget()).getInstrInfo();
- TD = ((X86TargetMachine&)MF.getTarget()).getTargetData();
- Is64BitMode =
- ((X86TargetMachine&)MF.getTarget()).getSubtarget<X86Subtarget>().is64Bit();
-
+
+ MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
+
+ II = TM.getInstrInfo();
+ TD = TM.getTargetData();
+ Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
+
do {
+ DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
MCE.startFunction(MF);
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
MBB != E; ++MBB) {
MCE.StartMachineBasicBlock(MBB);
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
- I != E; ++I)
- emitInstruction(*I);
+ I != E; ++I) {
+ const TargetInstrDesc &Desc = I->getDesc();
+ emitInstruction(*I, &Desc);
+ // MOVPC32r is basically a call plus a pop instruction.
+ if (Desc.getOpcode() == X86::MOVPC32r)
+ emitInstruction(*I, &II->get(X86::POP32r));
+ NumEmitted++; // Keep track of the # of mi's emitted
+ }
}
} while (MCE.finishFunction(MF));
return false;
}
-/// emitPCRelativeValue - Emit a PC relative address.
-///
-void Emitter::emitPCRelativeValue(intptr_t Address) {
- MCE.emitWordLE(Address-MCE.getCurrentPCValue()-4);
-}
-
/// emitPCRelativeBlockAddress - This method keeps track of the information
/// necessary to resolve the address of this block later and emits a dummy
/// value.
MCE.emitWordLE(0);
}
-/// emitGlobalAddressForCall - Emit the specified address to the code stream
-/// assuming this is part of a function call, which is PC relative.
-///
-void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
- X86::reloc_pcrel_word, GV, 0,
- DoesntNeedStub));
- MCE.emitWordLE(0);
-}
-
/// emitGlobalAddress - Emit the specified address to the code stream assuming
/// this is part of a "take the address of a global" instruction.
///
-void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
- int Disp /* = 0 */,
- unsigned PCAdj /* = 0 */) {
- MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
- GV, PCAdj));
+void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
+ int Disp /* = 0 */, intptr_t PCAdj /* = 0 */,
+ bool NeedStub /* = false */,
+ bool isLazy /* = false */) {
+ intptr_t RelocCST = 0;
+ if (Reloc == X86::reloc_picrel_word)
+ RelocCST = PICBaseOffset;
+ else if (Reloc == X86::reloc_pcrel_word)
+ RelocCST = PCAdj;
+ MachineRelocation MR = isLazy
+ ? MachineRelocation::getGVLazyPtr(MCE.getCurrentPCOffset(), Reloc,
+ GV, RelocCST, NeedStub)
+ : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
+ GV, RelocCST, NeedStub);
+ MCE.addRelocation(MR);
if (Reloc == X86::reloc_absolute_dword)
MCE.emitWordLE(0);
MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
+ intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
- Reloc, ES));
+ Reloc, ES, RelocCST));
if (Reloc == X86::reloc_absolute_dword)
MCE.emitWordLE(0);
MCE.emitWordLE(0);
/// relative.
void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
int Disp /* = 0 */,
- unsigned PCAdj /* = 0 */) {
+ intptr_t PCAdj /* = 0 */) {
+ intptr_t RelocCST = 0;
+ if (Reloc == X86::reloc_picrel_word)
+ RelocCST = PICBaseOffset;
+ else if (Reloc == X86::reloc_pcrel_word)
+ RelocCST = PCAdj;
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
- Reloc, CPI, PCAdj));
+ Reloc, CPI, RelocCST));
if (Reloc == X86::reloc_absolute_dword)
MCE.emitWordLE(0);
MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
/// be emitted to the current location in the function, and allow it to be PC
/// relative.
void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
- unsigned PCAdj /* = 0 */) {
+ intptr_t PCAdj /* = 0 */) {
+ intptr_t RelocCST = 0;
+ if (Reloc == X86::reloc_picrel_word)
+ RelocCST = PICBaseOffset;
+ else if (Reloc == X86::reloc_pcrel_word)
+ RelocCST = PCAdj;
MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
- Reloc, JTI, PCAdj));
+ Reloc, JTI, RelocCST));
if (Reloc == X86::reloc_absolute_dword)
MCE.emitWordLE(0);
MCE.emitWordLE(0); // The relocated value will be added to the displacement
}
-/// N86 namespace - Native X86 Register numbers... used by X86 backend.
-///
-namespace N86 {
- enum {
- EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
- };
-}
-
-// getX86RegNum - This function maps LLVM register identifiers to their X86
-// specific numbering, which is used in various places encoding instructions.
-//
-unsigned Emitter::getX86RegNum(unsigned RegNo) {
- switch(RegNo) {
- case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
- case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
- case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
- case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
- case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
- return N86::ESP;
- case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
- return N86::EBP;
- case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
- return N86::ESI;
- case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
- return N86::EDI;
-
- case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
- return N86::EAX;
- case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
- return N86::ECX;
- case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
- return N86::EDX;
- case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
- return N86::EBX;
- case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
- return N86::ESP;
- case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
- return N86::EBP;
- case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
- return N86::ESI;
- case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
- return N86::EDI;
-
- case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
- case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
- return RegNo-X86::ST0;
-
- case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
- case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7:
- return II->getRegisterInfo().getDwarfRegNum(RegNo) -
- II->getRegisterInfo().getDwarfRegNum(X86::XMM0);
- case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
- case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
- return II->getRegisterInfo().getDwarfRegNum(RegNo) -
- II->getRegisterInfo().getDwarfRegNum(X86::XMM8);
-
- default:
- assert(MRegisterInfo::isVirtualRegister(RegNo) &&
- "Unknown physical register!");
- assert(0 && "Register allocator hasn't allocated reg correctly yet!");
- return 0;
- }
+unsigned Emitter::getX86RegNum(unsigned RegNo) const {
+ return II->getRegisterInfo().getX86RegNum(RegNo);
}
inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
return Value == (signed char)Value;
}
+bool Emitter::gvNeedsLazyPtr(const GlobalValue *GV) {
+ return !Is64BitMode &&
+ TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
+}
+
void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
- int DispVal, unsigned PCAdj) {
+ int DispVal, intptr_t PCAdj) {
// If this is a simple integer displacement that doesn't require a relocation,
// emit it now.
if (!RelocOp) {
if (RelocOp->isGlobalAddress()) {
// In 64-bit static small code model, we could potentially emit absolute.
// But it's probably not beneficial.
- // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
- // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
- unsigned rt= Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
- emitGlobalAddressForPtr(RelocOp->getGlobal(), rt,
- RelocOp->getOffset(), PCAdj);
+ // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
+ // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
+ bool NeedStub = isa<Function>(RelocOp->getGlobal());
+ bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal());
+ emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
+ PCAdj, NeedStub, isLazy);
} else if (RelocOp->isConstantPoolIndex()) {
- // Must be in 64-bit mode.
- emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word,
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
+ emitConstPoolAddress(RelocOp->getIndex(), rt,
RelocOp->getOffset(), PCAdj);
} else if (RelocOp->isJumpTableIndex()) {
- // Must be in 64-bit mode.
- emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word,
- PCAdj);
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
+ emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
} else {
assert(0 && "Unknown value to relocate!");
}
void Emitter::emitMemModRMByte(const MachineInstr &MI,
unsigned Op, unsigned RegOpcodeField,
- unsigned PCAdj) {
+ intptr_t PCAdj) {
const MachineOperand &Op3 = MI.getOperand(Op+3);
int DispVal = 0;
const MachineOperand *DispForReloc = 0;
if (Op3.isGlobalAddress()) {
DispForReloc = &Op3;
} else if (Op3.isConstantPoolIndex()) {
- if (Is64BitMode) {
+ if (Is64BitMode || IsPIC) {
DispForReloc = &Op3;
} else {
- DispVal += MCE.getConstantPoolEntryAddress(Op3.getConstantPoolIndex());
+ DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
DispVal += Op3.getOffset();
}
} else if (Op3.isJumpTableIndex()) {
- if (Is64BitMode) {
+ if (Is64BitMode || IsPIC) {
DispForReloc = &Op3;
} else {
- DispVal += MCE.getJumpTableEntryAddress(Op3.getJumpTableIndex());
+ DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
}
} else {
DispVal = Op3.getImm();
}
}
-static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
- switch (Desc->TSFlags & X86II::ImmMask) {
- case X86II::Imm8: return 1;
- case X86II::Imm16: return 2;
- case X86II::Imm32: return 4;
- case X86II::Imm64: return 8;
- default: assert(0 && "Immediate size not set!");
- return 0;
- }
-}
-
-/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
-/// e.g. r8, xmm8, etc.
-bool Emitter::isX86_64ExtendedReg(const MachineOperand &MO) {
- if (!MO.isRegister()) return false;
- unsigned RegNo = MO.getReg();
- int DWNum = II->getRegisterInfo().getDwarfRegNum(RegNo);
- if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::R8) &&
- DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::R15))
- return true;
- if (DWNum >= II->getRegisterInfo().getDwarfRegNum(X86::XMM8) &&
- DWNum <= II->getRegisterInfo().getDwarfRegNum(X86::XMM15))
- return true;
- return false;
-}
-
-inline static bool isX86_64TruncToByte(unsigned oc) {
- return (oc == X86::TRUNC_64to8 || oc == X86::TRUNC_32to8 ||
- oc == X86::TRUNC_16to8);
-}
-
-
-inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
- return (reg == X86::SPL || reg == X86::BPL ||
- reg == X86::SIL || reg == X86::DIL);
-}
+void Emitter::emitInstruction(const MachineInstr &MI,
+ const TargetInstrDesc *Desc) {
+ DOUT << MI;
-/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
-/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
-/// size, and 3) use of X86-64 extended registers.
-unsigned Emitter::determineREX(const MachineInstr &MI) {
- unsigned REX = 0;
- const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
unsigned Opcode = Desc->Opcode;
- // Pseudo instructions do not need REX prefix byte.
- if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
- return 0;
- if (Desc->TSFlags & X86II::REX_W)
- REX |= 1 << 3;
-
- unsigned NumOps = Desc->numOperands;
- if (NumOps) {
- bool isTwoAddr = NumOps > 1 &&
- Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
-
- // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
- bool isTrunc8 = isX86_64TruncToByte(Opcode);
- unsigned i = isTwoAddr ? 1 : 0;
- for (unsigned e = NumOps; i != e; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (MO.isRegister()) {
- unsigned Reg = MO.getReg();
- // Trunc to byte are actually movb. The real source operand is the low
- // byte of the register.
- if (isTrunc8 && i == 1)
- Reg = getX86SubSuperRegister(Reg, MVT::i8);
- if (isX86_64NonExtLowByteReg(Reg))
- REX |= 0x40;
- }
- }
-
- switch (Desc->TSFlags & X86II::FormMask) {
- case X86II::MRMInitReg:
- if (isX86_64ExtendedReg(MI.getOperand(0)))
- REX |= (1 << 0) | (1 << 2);
- break;
- case X86II::MRMSrcReg: {
- if (isX86_64ExtendedReg(MI.getOperand(0)))
- REX |= 1 << 2;
- i = isTwoAddr ? 2 : 1;
- for (unsigned e = NumOps; i != e; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (isX86_64ExtendedReg(MO))
- REX |= 1 << 0;
- }
- break;
- }
- case X86II::MRMSrcMem: {
- if (isX86_64ExtendedReg(MI.getOperand(0)))
- REX |= 1 << 2;
- unsigned Bit = 0;
- i = isTwoAddr ? 2 : 1;
- for (; i != NumOps; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (MO.isRegister()) {
- if (isX86_64ExtendedReg(MO))
- REX |= 1 << Bit;
- Bit++;
- }
- }
- break;
- }
- case X86II::MRM0m: case X86II::MRM1m:
- case X86II::MRM2m: case X86II::MRM3m:
- case X86II::MRM4m: case X86II::MRM5m:
- case X86II::MRM6m: case X86II::MRM7m:
- case X86II::MRMDestMem: {
- unsigned e = isTwoAddr ? 5 : 4;
- i = isTwoAddr ? 1 : 0;
- if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
- REX |= 1 << 2;
- unsigned Bit = 0;
- for (; i != e; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (MO.isRegister()) {
- if (isX86_64ExtendedReg(MO))
- REX |= 1 << Bit;
- Bit++;
- }
- }
- break;
- }
- default: {
- if (isX86_64ExtendedReg(MI.getOperand(0)))
- REX |= 1 << 0;
- i = isTwoAddr ? 2 : 1;
- for (unsigned e = NumOps; i != e; ++i) {
- const MachineOperand& MO = MI.getOperand(i);
- if (isX86_64ExtendedReg(MO))
- REX |= 1 << 2;
- }
- break;
- }
- }
- }
- return REX;
-}
-
-void Emitter::emitInstruction(const MachineInstr &MI) {
- NumEmitted++; // Keep track of the # of mi's emitted
-
- const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
- unsigned Opcode = Desc->Opcode;
+ // Emit the lock opcode prefix as needed.
+ if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
// Emit the repeat opcode prefix as needed.
if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
bool Need0FPrefix = false;
switch (Desc->TSFlags & X86II::Op0Mask) {
- case X86II::TB:
- Need0FPrefix = true; // Two-byte opcode prefix
- break;
- case X86II::T8:
- MCE.emitByte(0x0F);
- MCE.emitByte(0x38);
- break;
- case X86II::TA:
- MCE.emitByte(0x0F);
- MCE.emitByte(0x3A);
+ case X86II::TB: // Two-byte opcode prefix
+ case X86II::T8: // 0F 38
+ case X86II::TA: // 0F 3A
+ Need0FPrefix = true;
break;
case X86II::REP: break; // already handled.
case X86II::XS: // F3 0F
if (Is64BitMode) {
// REX prefix
- unsigned REX = determineREX(MI);
+ unsigned REX = X86InstrInfo::determineREX(MI);
if (REX)
MCE.emitByte(0x40 | REX);
}
if (Need0FPrefix)
MCE.emitByte(0x0F);
+ switch (Desc->TSFlags & X86II::Op0Mask) {
+ case X86II::T8: // 0F 38
+ MCE.emitByte(0x38);
+ break;
+ case X86II::TA: // 0F 3A
+ MCE.emitByte(0x3A);
+ break;
+ }
+
// If this is a two-address instruction, skip one of the register operands.
- unsigned NumOps = Desc->numOperands;
+ unsigned NumOps = Desc->getNumOperands();
unsigned CurOp = 0;
if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
- CurOp++;
+ ++CurOp;
+ else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
+ // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
+ --NumOps;
unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
switch (Desc->TSFlags & X86II::FormMask) {
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
-#ifndef NDEBUG
+ // Remember the current PC offset, this is the PIC relocation
+ // base address.
switch (Opcode) {
default:
assert(0 && "psuedo instructions should be removed before code emission");
+ break;
case TargetInstrInfo::INLINEASM:
assert(0 && "JIT does not support inline asm!\n");
+ break;
case TargetInstrInfo::LABEL:
- assert(0 && "JIT does not support meta labels!\n");
- case X86::IMPLICIT_USE:
- case X86::IMPLICIT_DEF:
- case X86::IMPLICIT_DEF_GR8:
- case X86::IMPLICIT_DEF_GR16:
- case X86::IMPLICIT_DEF_GR32:
- case X86::IMPLICIT_DEF_GR64:
- case X86::IMPLICIT_DEF_FR32:
- case X86::IMPLICIT_DEF_FR64:
- case X86::IMPLICIT_DEF_VR64:
- case X86::IMPLICIT_DEF_VR128:
+ MCE.emitLabel(MI.getOperand(0).getImm());
+ break;
+ case TargetInstrInfo::IMPLICIT_DEF:
+ case TargetInstrInfo::DECLARE:
+ case X86::DWARF_LOC:
case X86::FP_REG_KILL:
break;
+ case X86::MOVPC32r: {
+ // This emits the "call" portion of this pseudo instruction.
+ MCE.emitByte(BaseOpcode);
+ emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
+ // Remember PIC base.
+ PICBaseOffset = MCE.getCurrentPCOffset();
+ X86JITInfo *JTI = TM.getJITInfo();
+ JTI->setPICBase(MCE.getCurrentPCValue());
+ break;
+ }
}
-#endif
CurOp = NumOps;
break;
-
case X86II::RawFrm:
MCE.emitByte(BaseOpcode);
+
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
if (MO.isMachineBasicBlock()) {
- emitPCRelativeBlockAddress(MO.getMachineBasicBlock());
+ emitPCRelativeBlockAddress(MO.getMBB());
} else if (MO.isGlobalAddress()) {
- bool NeedStub = Is64BitMode ||
- Opcode == X86::TAILJMPd ||
- Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
- emitGlobalAddressForCall(MO.getGlobal(), !NeedStub);
+ bool NeedStub = (Is64BitMode && TM.getCodeModel() == CodeModel::Large)
+ || Opcode == X86::TAILJMPd;
+ emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
+ 0, 0, NeedStub);
} else if (MO.isExternalSymbol()) {
emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
} else if (MO.isImmediate()) {
- emitConstant(MO.getImm(), sizeOfImm(Desc));
+ emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
} else {
assert(0 && "Unknown RawFrm operand!");
}
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
- unsigned Size = sizeOfImm(Desc);
+ unsigned Size = X86InstrInfo::sizeOfImm(Desc);
if (MO1.isImmediate())
emitConstant(MO1.getImm(), Size);
else {
- unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
+ unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
if (Opcode == X86::MOV64ri)
rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
- if (MO1.isGlobalAddress())
- emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
- else if (MO1.isExternalSymbol())
+ if (MO1.isGlobalAddress()) {
+ bool NeedStub = isa<Function>(MO1.getGlobal());
+ bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
+ emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
+ NeedStub, isLazy);
+ } else if (MO1.isExternalSymbol())
emitExternalSymbolAddress(MO1.getSymbolName(), rt);
else if (MO1.isConstantPoolIndex())
- emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
+ emitConstPoolAddress(MO1.getIndex(), rt);
else if (MO1.isJumpTableIndex())
- emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
+ emitJumpTableAddress(MO1.getIndex(), rt);
}
}
break;
getX86RegNum(MI.getOperand(CurOp+1).getReg()));
CurOp += 2;
if (CurOp != NumOps)
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
}
case X86II::MRMDestMem: {
emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
CurOp += 5;
if (CurOp != NumOps)
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
}
getX86RegNum(MI.getOperand(CurOp).getReg()));
CurOp += 2;
if (CurOp != NumOps)
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
case X86II::MRMSrcMem: {
- unsigned PCAdj = (CurOp+5 != NumOps) ? sizeOfImm(Desc) : 0;
+ intptr_t PCAdj = (CurOp+5 != NumOps) ? X86InstrInfo::sizeOfImm(Desc) : 0;
MCE.emitByte(BaseOpcode);
emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
PCAdj);
CurOp += 5;
if (CurOp != NumOps)
- emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
+ emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
break;
}
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
- unsigned Size = sizeOfImm(Desc);
+ unsigned Size = X86InstrInfo::sizeOfImm(Desc);
if (MO1.isImmediate())
emitConstant(MO1.getImm(), Size);
else {
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
- : X86::reloc_absolute_word;
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
if (Opcode == X86::MOV64ri32)
rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
- if (MO1.isGlobalAddress())
- emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
- else if (MO1.isExternalSymbol())
+ if (MO1.isGlobalAddress()) {
+ bool NeedStub = isa<Function>(MO1.getGlobal());
+ bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
+ emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
+ NeedStub, isLazy);
+ } else if (MO1.isExternalSymbol())
emitExternalSymbolAddress(MO1.getSymbolName(), rt);
else if (MO1.isConstantPoolIndex())
- emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
+ emitConstPoolAddress(MO1.getIndex(), rt);
else if (MO1.isJumpTableIndex())
- emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
+ emitJumpTableAddress(MO1.getIndex(), rt);
}
}
break;
case X86II::MRM2m: case X86II::MRM3m:
case X86II::MRM4m: case X86II::MRM5m:
case X86II::MRM6m: case X86II::MRM7m: {
- unsigned PCAdj = (CurOp+4 != NumOps) ?
- (MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
+ intptr_t PCAdj = (CurOp+4 != NumOps) ?
+ (MI.getOperand(CurOp+4).isImmediate() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
MCE.emitByte(BaseOpcode);
emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
- unsigned Size = sizeOfImm(Desc);
+ unsigned Size = X86InstrInfo::sizeOfImm(Desc);
if (MO.isImmediate())
emitConstant(MO.getImm(), Size);
else {
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
- : X86::reloc_absolute_word;
+ : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
if (Opcode == X86::MOV64mi32)
rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
- if (MO.isGlobalAddress())
- emitGlobalAddressForPtr(MO.getGlobal(), rt, MO.getOffset());
- else if (MO.isExternalSymbol())
+ if (MO.isGlobalAddress()) {
+ bool NeedStub = isa<Function>(MO.getGlobal());
+ bool isLazy = gvNeedsLazyPtr(MO.getGlobal());
+ emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
+ NeedStub, isLazy);
+ } else if (MO.isExternalSymbol())
emitExternalSymbolAddress(MO.getSymbolName(), rt);
else if (MO.isConstantPoolIndex())
- emitConstPoolAddress(MO.getConstantPoolIndex(), rt);
+ emitConstPoolAddress(MO.getIndex(), rt);
else if (MO.isJumpTableIndex())
- emitJumpTableAddress(MO.getJumpTableIndex(), rt);
+ emitJumpTableAddress(MO.getIndex(), rt);
}
}
break;
break;
}
- assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
- CurOp == NumOps && "Unknown encoding!");
+ if (!Desc->isVariadic() && CurOp != NumOps) {
+ cerr << "Cannot encode: ";
+ MI.dump();
+ cerr << '\n';
+ abort();
+ }
}
projects / oota-llvm.git / blobdiff