remove MachineOpCode typedef.

[oota-llvm.git] / lib / Target / X86 / X86CallingConv.td

diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td
index f23e5806563725d1c4a77afcdae44d0655cfd36a..3a940003a3b6fcf00e96b887ee30d1127e99c5e4 100644 (file)
--- a/lib/Target/X86/X86CallingConv.td
+++ b/lib/Target/X86/X86CallingConv.td
@@ -1,9 +1,9 @@
-//===- X86CallingConv.td - Calling Conventions for X86 32/64 ----*- C++ -*-===//
+//===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by Chris Lattner and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -52,10 +52,12 @@ def RetCC_X86_32_C : CallingConv<[
 
 // X86-32 FastCC return-value convention.
 def RetCC_X86_32_Fast : CallingConv<[
-  // The X86-32 fastcc returns FP values in XMM0 if the target has SSE2,
-  // otherwise it is the the C calling conventions.
-  CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>,
-  CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>,
+  // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
+  // SSE2, otherwise it is the the C calling conventions.
+  // This can happen when a float, 2 x float, or 3 x float vector is split by
+  // target lowering, and is returned in 1-3 sse regs.
+  CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
+  CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
   CCDelegateTo<RetCC_X86Common>
 ]>;
 
@@ -118,16 +120,18 @@ def CC_X86_64_C : CallingConv<[
   // 8-byte aligned if there are no more registers to hold them.
   CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
   
-  // Long doubles get 16-byte stack slots that are 16-byte aligned.
+  // Long doubles get stack slots whose size and alignment depends on the
+  // subtarget.
+  CCIfType<[f80], CCAssignToStack<0, 0>>,
+
   // Vectors get 16-byte stack slots that are 16-byte aligned.
-  CCIfType<[f80, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 
-              CCAssignToStack<16, 16>>,
+  CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
 
   // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
   CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
 ]>;
 
-// tail call convetion (fast) one register is reserved for target address
+// Tail call convention (fast): One register is reserved for target address,
 // namely R9
 def CC_X86_64_TailCall : CallingConv<[
   // Promote i8/i16 arguments to i32.
@@ -177,7 +181,8 @@ def CC_X86_32_Common : CallingConv<[
   // Doubles get 8-byte slots that are 4-byte aligned.
   CCIfType<[f64], CCAssignToStack<8, 4>>,
 
-  // Long doubles get 16-byte slots that are 4-byte aligned.
+  // Long doubles get slots whose size and alignment depends on the
+  // subtarget.
   CCIfType<[f80], CCAssignToStack<16, 4>>,
 
   // The first 4 vector arguments are passed in XMM registers.
@@ -207,15 +212,14 @@ def CC_X86_32_C : CallingConv<[
   CCDelegateTo<CC_X86_32_Common>
 ]>;
 
-/// Same as C calling convention up to nonfree ECX which is used for storing 
-/// potential pointer to tail called function
+/// Same as C calling convention except for non-free ECX which is used for storing 
+/// a potential pointer to the tail called function.
 def CC_X86_32_TailCall : CallingConv<[
   // Promote i8/i16 arguments to i32.
   CCIfType<[i8, i16], CCPromoteToType<i32>>,
 
-  // The 'nest' parameter, if any, is passed in ECX.
-  CCIfNest<CCAssignToReg<[ECX]>>,
-
+  // Nested function trampolines are currently not supported by fastcc.
+  
   // The first 3 integer arguments, if marked 'inreg' and if the call is not
   // a vararg call, are passed in integer registers.
   CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>>>,