-//===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
+//===-- X86AsmPrinter.cpp - Convert X86 LLVM IR to X86 assembly -----------===//
//
-// This file contains a printer that converts from our internal representation
-// of LLVM code to a nice human readable form that is suitable for debuggging.
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file the shared super class printer that converts from our internal
+// representation of machine-dependent LLVM code to Intel and AT&T format
+// assembly language.
+// This printer is the output mechanism used by `llc'.
//
//===----------------------------------------------------------------------===//
+#include "X86ATTAsmPrinter.h"
+#include "X86IntelAsmPrinter.h"
#include "X86.h"
-#include "X86InstrInfo.h"
-#include "llvm/Pass.h"
-#include "llvm/Function.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "Support/Statistic.h"
-
-namespace {
- struct Printer : public FunctionPass {
- TargetMachine &TM;
- std::ostream &O;
-
- Printer(TargetMachine &tm, std::ostream &o) : TM(tm), O(o) {}
-
- virtual const char *getPassName() const {
- return "X86 Assembly Printer";
- }
-
- bool runOnFunction(Function &F);
- };
-}
-
-/// createX86CodePrinterPass - Print out the specified machine code function to
-/// the specified stream. This function should work regardless of whether or
-/// not the function is in SSA form or not.
-///
-Pass *createX86CodePrinterPass(TargetMachine &TM, std::ostream &O) {
- return new Printer(TM, O);
-}
-
-
-/// runOnFunction - This uses the X86InstructionInfo::print method
-/// to print assembly for each instruction.
-bool Printer::runOnFunction (Function & F)
-{
- static unsigned bbnumber = 0;
- MachineFunction & MF = MachineFunction::get (&F);
- const MachineInstrInfo & MII = TM.getInstrInfo ();
-
- // Print out labels for the function.
- O << "\t.globl\t" << F.getName () << "\n";
- O << "\t.type\t" << F.getName () << ", @function\n";
- O << F.getName () << ":\n";
-
- // Print out code for the function.
- for (MachineFunction::const_iterator bb_i = MF.begin (), bb_e = MF.end ();
- bb_i != bb_e; ++bb_i)
- {
- // Print a label for the basic block.
- O << ".BB" << bbnumber++ << ":\n";
- for (MachineBasicBlock::const_iterator i_i = bb_i->begin (), i_e =
- bb_i->end (); i_i != i_e; ++i_i)
- {
- // Print the assembly for the instruction.
- O << "\t";
- MII.print(*i_i, O, TM);
- }
- }
-
- // We didn't modify anything.
- return false;
-}
-
-static bool isScale(const MachineOperand &MO) {
- return MO.isImmediate() &&
- (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
- MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
-}
-
-static bool isMem(const MachineInstr *MI, unsigned Op) {
- return Op+4 <= MI->getNumOperands() &&
- MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
- MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
-}
+#include "llvm/Module.h"
+#include "llvm/Type.h"
+#include "llvm/Assembly/Writer.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/Support/Mangler.h"
+#include "llvm/Support/CommandLine.h"
+using namespace llvm;
+using namespace x86;
+
+Statistic<> llvm::x86::EmittedInsts("asm-printer",
+ "Number of machine instrs printed");
+
+enum AsmWriterFlavorTy { att, intel };
+cl::opt<AsmWriterFlavorTy>
+AsmWriterFlavor("x86-asm-syntax",
+ cl::desc("Choose style of code to emit from X86 backend:"),
+ cl::values(
+ clEnumVal(att, " Emit AT&T-style assembly"),
+ clEnumVal(intel, " Emit Intel-style assembly"),
+ clEnumValEnd),
+ cl::init(att));
+
+/// doInitialization
+bool X86SharedAsmPrinter::doInitialization(Module& M) {
+ bool leadingUnderscore = false;
+ forCygwin = false;
+ const std::string& TT = M.getTargetTriple();
+ if (TT.length() > 5) {
+ forCygwin = TT.find("cygwin") != std::string::npos ||
+ TT.find("mingw") != std::string::npos;
+ forDarwin = TT.find("darwin") != std::string::npos;
+ } else if (TT.empty()) {
+#if defined(__CYGWIN__) || defined(__MINGW32__)
+ forCygwin = true;
+#elif defined(__APPLE__)
+ forDarwin = true;
+#elif defined(_WIN32)
+ leadingUnderscore = true;
+#else
+ leadingUnderscore = false;
+#endif
+ }
-static void printOp(std::ostream &O, const MachineOperand &MO,
- const MRegisterInfo &RI) {
- switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- case MachineOperand::MO_MachineRegister:
- if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
- O << RI.get(MO.getReg()).Name;
- else
- O << "%reg" << MO.getReg();
- return;
+ if (leadingUnderscore || forCygwin || forDarwin)
+ GlobalPrefix = "_";
- case MachineOperand::MO_SignExtendedImmed:
- case MachineOperand::MO_UnextendedImmed:
- O << (int)MO.getImmedValue();
- return;
- case MachineOperand::MO_PCRelativeDisp:
- O << "<" << MO.getVRegValue()->getName() << ">";
- return;
- default:
- O << "<unknown op ty>"; return;
+ if (forDarwin) {
+ AlignmentIsInBytes = false;
+ Data64bitsDirective = 0; // we can't emit a 64-bit unit
+ ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
+ PrivateGlobalPrefix = "L"; // Marker for constant pool idxs
}
-}
-static const std::string sizePtr (const MachineInstrDescriptor &Desc) {
- switch (Desc.TSFlags & X86II::ArgMask) {
- case X86II::Arg8: return "BYTE PTR";
- case X86II::Arg16: return "WORD PTR";
- case X86II::Arg32: return "DWORD PTR";
- case X86II::Arg64: return "QWORD PTR";
- case X86II::Arg80: return "XWORD PTR";
- case X86II::Arg128: return "128BIT PTR"; // dunno what the real one is
- default: return "<SIZE?> PTR"; // crack being smoked
- }
+ return AsmPrinter::doInitialization(M);
}
-static void printMemReference(std::ostream &O, const MachineInstr *MI,
- unsigned Op, const MRegisterInfo &RI) {
- assert(isMem(MI, Op) && "Invalid memory reference!");
- const MachineOperand &BaseReg = MI->getOperand(Op);
- const MachineOperand &Scale = MI->getOperand(Op+1);
- const MachineOperand &IndexReg = MI->getOperand(Op+2);
- const MachineOperand &Disp = MI->getOperand(Op+3);
+/// printConstantPool - Print to the current output stream assembly
+/// representations of the constants in the constant pool MCP. This is
+/// used to print out constants which have been "spilled to memory" by
+/// the code generator.
+///
+void X86SharedAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
+ const std::vector<Constant*> &CP = MCP->getConstants();
+ const TargetData &TD = TM.getTargetData();
- O << "[";
- bool NeedPlus = false;
- if (BaseReg.getReg()) {
- printOp(O, BaseReg, RI);
- NeedPlus = true;
- }
+ if (CP.empty()) return;
- if (IndexReg.getReg()) {
- if (NeedPlus) O << " + ";
- if (Scale.getImmedValue() != 1)
- O << Scale.getImmedValue() << "*";
- printOp(O, IndexReg, RI);
- NeedPlus = true;
+ if (forDarwin) {
+ O << "\t.const\n";
+ } else {
+ O << "\t.section .rodata\n";
}
-
- if (Disp.getImmedValue()) {
- if (NeedPlus) O << " + ";
- printOp(O, Disp, RI);
+
+ for (unsigned i = 0, e = CP.size(); i != e; ++i) {
+ // FIXME: force doubles to be naturally aligned. We should handle this
+ // more correctly in the future.
+ if (CP[i]->getType() == Type::DoubleTy)
+ emitAlignment(3);
+ else
+ emitAlignment(TD.getTypeAlignmentShift(CP[i]->getType()));
+ O << PrivateGlobalPrefix << "CPI" << CurrentFnName << "_" << i
+ << ":\t\t\t\t\t" << CommentString << *CP[i] << "\n";
+ emitGlobalConstant(CP[i]);
}
- O << "]";
}
-// print - Print out an x86 instruction in intel syntax
-void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
- const TargetMachine &TM) const {
- unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = get(Opcode);
-
- if (Opcode == X86::PHI) {
- printOp(O, MI->getOperand(0), RI);
- O << " = phi ";
- for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
- if (i != 1) O << ", ";
- O << "[";
- printOp(O, MI->getOperand(i), RI);
- O << ", ";
- printOp(O, MI->getOperand(i+1), RI);
- O << "]";
+bool X86SharedAsmPrinter::doFinalization(Module &M) {
+ const TargetData &TD = TM.getTargetData();
+ std::string CurSection;
+
+ // Print out module-level global variables here.
+ for (Module::const_global_iterator I = M.global_begin(),
+ E = M.global_end(); I != E; ++I)
+ if (I->hasInitializer()) { // External global require no code
+ O << "\n\n";
+ std::string name = Mang->getValueName(I);
+ Constant *C = I->getInitializer();
+ unsigned Size = TD.getTypeSize(C->getType());
+ unsigned Align = TD.getTypeAlignmentShift(C->getType());
+
+ if (C->isNullValue() &&
+ (I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
+ I->hasWeakLinkage() /* FIXME: Verify correct */)) {
+ switchSection(O, CurSection, ".data");
+ if (!forCygwin && !forDarwin && I->hasInternalLinkage())
+ O << "\t.local " << name << "\n";
+ if (forDarwin && I->hasInternalLinkage())
+ O << "\t.lcomm " << name << "," << Size << "," << Align;
+ else
+ O << "\t.comm " << name << "," << Size;
+ if (!forCygwin && !forDarwin)
+ O << "," << (1 << Align);
+ O << "\t\t# ";
+ WriteAsOperand(O, I, true, true, &M);
+ O << "\n";
+ } else {
+ switch (I->getLinkage()) {
+ default: assert(0 && "Unknown linkage type!");
+ case GlobalValue::LinkOnceLinkage:
+ case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak.
+ // Nonnull linkonce -> weak
+ O << "\t.weak " << name << "\n";
+ switchSection(O, CurSection, "");
+ O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n";
+ break;
+ case GlobalValue::AppendingLinkage:
+ // FIXME: appending linkage variables should go into a section of
+ // their name or something. For now, just emit them as external.
+ case GlobalValue::ExternalLinkage:
+ // If external or appending, declare as a global symbol
+ O << "\t.globl " << name << "\n";
+ // FALL THROUGH
+ case GlobalValue::InternalLinkage:
+ if (C->isNullValue())
+ switchSection(O, CurSection, ".bss");
+ else
+ switchSection(O, CurSection, ".data");
+ break;
+ }
+
+ emitAlignment(Align);
+ if (!forCygwin && !forDarwin) {
+ O << "\t.type " << name << ",@object\n";
+ O << "\t.size " << name << "," << Size << "\n";
+ }
+ O << name << ":\t\t\t\t# ";
+ WriteAsOperand(O, I, true, true, &M);
+ O << " = ";
+ WriteAsOperand(O, C, false, false, &M);
+ O << "\n";
+ emitGlobalConstant(C);
+ }
}
- O << "\n";
- return;
- }
-
- switch (Desc.TSFlags & X86II::FormMask) {
- case X86II::RawFrm:
- // The accepted forms of Raw instructions are:
- // 1. nop - No operand required
- // 2. jmp foo - PC relative displacement operand
- //
- assert(MI->getNumOperands() == 0 ||
- (MI->getNumOperands() == 1 && MI->getOperand(0).isPCRelativeDisp())&&
- "Illegal raw instruction!");
- O << getName(MI->getOpCode()) << " ";
-
- if (MI->getNumOperands() == 1) {
- printOp(O, MI->getOperand(0), RI);
+ if (forDarwin) {
+ // Output stubs for external global variables
+ if (GVStubs.begin() != GVStubs.end())
+ O << "\t.non_lazy_symbol_pointer\n";
+ for (std::set<std::string>::iterator i = GVStubs.begin(), e = GVStubs.end();
+ i != e; ++i) {
+ O << "L" << *i << "$non_lazy_ptr:\n";
+ O << "\t.indirect_symbol " << *i << "\n";
+ O << "\t.long\t0\n";
}
- O << "\n";
- return;
- case X86II::AddRegFrm: {
- // There are currently two forms of acceptable AddRegFrm instructions.
- // Either the instruction JUST takes a single register (like inc, dec, etc),
- // or it takes a register and an immediate of the same size as the register
- // (move immediate f.e.). Note that this immediate value might be stored as
- // an LLVM value, to represent, for example, loading the address of a global
- // into a register.
- //
- assert(MI->getOperand(0).isRegister() &&
- (MI->getNumOperands() == 1 ||
- (MI->getNumOperands() == 2 &&
- (MI->getOperand(1).getVRegValueOrNull() ||
- MI->getOperand(1).isImmediate()))) &&
- "Illegal form for AddRegFrm instruction!");
-
- unsigned Reg = MI->getOperand(0).getReg();
-
- O << getName(MI->getOpCode()) << " ";
- printOp(O, MI->getOperand(0), RI);
- if (MI->getNumOperands() == 2) {
- O << ", ";
- printOp(O, MI->getOperand(1), RI);
+ // Output stubs for dynamically-linked functions
+ unsigned j = 1;
+ for (std::set<std::string>::iterator i = FnStubs.begin(), e = FnStubs.end();
+ i != e; ++i, ++j) {
+ O << "\t.symbol_stub\n";
+ O << "L" << *i << "$stub:\n";
+ O << "\t.indirect_symbol " << *i << "\n";
+ O << "\tjmp\t*L" << j << "$lz\n";
+ O << "L" << *i << "$stub_binder:\n";
+ O << "\tpushl\t$L" << j << "$lz\n";
+ O << "\tjmp\tdyld_stub_binding_helper\n";
+ O << "\t.section __DATA, __la_sym_ptr3,lazy_symbol_pointers\n";
+ O << "L" << j << "$lz:\n";
+ O << "\t.indirect_symbol " << *i << "\n";
+ O << "\t.long\tL" << *i << "$stub_binder\n";
}
- O << "\n";
- return;
- }
- case X86II::MRMDestReg: {
- // There are two acceptable forms of MRMDestReg instructions, those with 3
- // and 2 operands:
- //
- // 3 Operands: in this form, the first two registers (the destination, and
- // the first operand) should be the same, post register allocation. The 3rd
- // operand is an additional input. This should be for things like add
- // instructions.
- //
- // 2 Operands: this is for things like mov that do not read a second input
- //
- assert(MI->getOperand(0).isRegister() &&
- (MI->getNumOperands() == 2 ||
- (MI->getNumOperands() == 3 && MI->getOperand(1).isRegister())) &&
- MI->getOperand(MI->getNumOperands()-1).isRegister()
- && "Bad format for MRMDestReg!");
- if (MI->getNumOperands() == 3 &&
- MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
- O << "**";
-
- O << getName(MI->getOpCode()) << " ";
- printOp(O, MI->getOperand(0), RI);
- O << ", ";
- printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
- O << "\n";
- return;
- }
- case X86II::MRMDestMem: {
- // These instructions are the same as MRMDestReg, but instead of having a
- // register reference for the mod/rm field, it's a memory reference.
- //
- assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
- MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
-
- O << getName(MI->getOpCode()) << " " << sizePtr (Desc) << " ";
- printMemReference(O, MI, 0, RI);
- O << ", ";
- printOp(O, MI->getOperand(4), RI);
O << "\n";
- return;
- }
- case X86II::MRMSrcReg: {
- // There is a two forms that are acceptable for MRMSrcReg instructions,
- // those with 3 and 2 operands:
- //
- // 3 Operands: in this form, the last register (the second input) is the
- // ModR/M input. The first two operands should be the same, post register
- // allocation. This is for things like: add r32, r/m32
- //
- // 2 Operands: this is for things like mov that do not read a second input
- //
- assert(MI->getOperand(0).isRegister() &&
- MI->getOperand(1).isRegister() &&
- (MI->getNumOperands() == 2 ||
- (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
- && "Bad format for MRMDestReg!");
- if (MI->getNumOperands() == 3 &&
- MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
- O << "**";
-
- O << getName(MI->getOpCode()) << " ";
- printOp(O, MI->getOperand(0), RI);
- O << ", ";
- printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
- O << "\n";
- return;
- }
-
- case X86II::MRMSrcMem: {
- // These instructions are the same as MRMSrcReg, but instead of having a
- // register reference for the mod/rm field, it's a memory reference.
- //
- assert(MI->getOperand(0).isRegister() &&
- (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
- (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
- isMem(MI, 2))
- && "Bad format for MRMDestReg!");
- if (MI->getNumOperands() == 2+4 &&
- MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
- O << "**";
-
- O << getName(MI->getOpCode()) << " ";
- printOp(O, MI->getOperand(0), RI);
- O << ", " << sizePtr (Desc) << " ";
- printMemReference(O, MI, MI->getNumOperands()-4, RI);
- O << "\n";
- return;
- }
-
- case X86II::MRMS0r: case X86II::MRMS1r:
- case X86II::MRMS2r: case X86II::MRMS3r:
- case X86II::MRMS4r: case X86II::MRMS5r:
- case X86II::MRMS6r: case X86II::MRMS7r: {
- // In this form, the following are valid formats:
- // 1. sete r
- // 2. cmp reg, immediate
- // 2. shl rdest, rinput <implicit CL or 1>
- // 3. sbb rdest, rinput, immediate [rdest = rinput]
- //
- assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
- MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
- assert((MI->getNumOperands() != 2 ||
- MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
- "Bad MRMSxR format!");
- assert((MI->getNumOperands() < 3 ||
- (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
- "Bad MRMSxR format!");
-
- if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
- MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
- O << "**";
-
- O << getName(MI->getOpCode()) << " ";
- printOp(O, MI->getOperand(0), RI);
- if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
- O << ", ";
- printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
+ // Output stubs for link-once variables
+ if (LinkOnceStubs.begin() != LinkOnceStubs.end())
+ O << ".data\n.align 2\n";
+ for (std::set<std::string>::iterator i = LinkOnceStubs.begin(),
+ e = LinkOnceStubs.end(); i != e; ++i) {
+ O << "L" << *i << "$non_lazy_ptr:\n"
+ << "\t.long\t" << *i << '\n';
}
- O << "\n";
-
- return;
}
+ AsmPrinter::doFinalization(M);
+ return false; // success
+}
+
+/// createX86CodePrinterPass - Returns a pass that prints the X86 assembly code
+/// for a MachineFunction to the given output stream, using the given target
+/// machine description.
+///
+FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){
+ switch (AsmWriterFlavor) {
default:
- O << "\t\t\t-"; MI->print(O, TM); break;
+ assert(0 && "Unknown asm flavor!");
+ case intel:
+ return new X86IntelAsmPrinter(o, tm);
+ case att:
+ return new X86ATTAsmPrinter(o, tm);
}
}
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