if (TAI->doesSupportDebugInformation()) {
// Let PassManager know we need debug information and relay
// the MachineModuleInfo address on to DwarfWriter.
- DW.SetModuleInfo(&getAnalysis<MachineModuleInfo>());
+ MMI = &getAnalysis<MachineModuleInfo>();
+ DW.SetModuleInfo(MMI);
}
SetupMachineFunction(MF);
O << "\t.weak_definition\t" << CurrentFnName << "\n";
} else if (Subtarget->isTargetCygMing()) {
EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
- O << "\t.globl " << CurrentFnName << "\n";
+ O << "\t.globl\t" << CurrentFnName << "\n";
O << "\t.linkonce discard\n";
} else {
EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
- O << "\t.weak " << CurrentFnName << "\n";
+ O << "\t.weak\t" << CurrentFnName << "\n";
}
break;
}
}
if (Subtarget->isTargetELF())
- O << "\t.type " << CurrentFnName << ",@function\n";
+ O << "\t.type\t" << CurrentFnName << ",@function\n";
else if (Subtarget->isTargetCygMing()) {
O << "\t.def\t " << CurrentFnName
<< ";\t.scl\t" <<
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block.
- if (I->pred_begin() != I->pred_end()) {
+ if (!I->pred_empty()) {
printBasicBlockLabel(I, true);
O << '\n';
}
}
if (TAI->hasDotTypeDotSizeDirective())
- O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
+ O << "\t.size\t" << CurrentFnName << ", .-" << CurrentFnName << "\n";
if (TAI->doesSupportDebugInformation()) {
// Emit post-function debug information.
O << "@GOT";
else
O << "@GOTOFF";
- } else if (Subtarget->isPICStyleRIPRel() && !NotRIPRel) {
+ } else if (Subtarget->isPICStyleRIPRel() && !NotRIPRel &&
+ TM.getRelocationModel() != Reloc::Static) {
if ((GV->isDeclaration() ||
GV->hasWeakLinkage() ||
GV->hasLinkOnceLinkage()) &&
case 'k': // Print SImode register
Reg = getX86SubSuperRegister(Reg, MVT::i32);
break;
+ case 'q': // Print DImode register
+ Reg = getX86SubSuperRegister(Reg, MVT::i64);
+ break;
}
O << '%';
case 'h': // Print QImode high register
case 'w': // Print HImode register
case 'k': // Print SImode register
- if (MI->getOperand(OpNo).isReg())
+ case 'q': // Print DImode register
+ if (MI->getOperand(OpNo).isRegister())
return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
printOperand(MI, OpNo);
return false;
unsigned OpNo,
unsigned AsmVariant,
const char *ExtraCode) {
- if (ExtraCode && ExtraCode[0])
- return true; // Unknown modifier.
+ if (ExtraCode && ExtraCode[0]) {
+ if (ExtraCode[1] != 0) return true; // Unknown modifier.
+
+ switch (ExtraCode[0]) {
+ default: return true; // Unknown modifier.
+ case 'b': // Print QImode register
+ case 'h': // Print QImode high register
+ case 'w': // Print HImode register
+ case 'k': // Print SImode register
+ case 'q': // Print SImode register
+ // These only apply to registers, ignore on mem.
+ break;
+ }
+ }
printMemReference(MI, OpNo);
return false;
}
// See if a truncate instruction can be turned into a nop.
switch (MI->getOpcode()) {
default: break;
- case X86::TRUNC_64to32:
- case X86::TRUNC_64to16:
- case X86::TRUNC_32to16:
- case X86::TRUNC_32to8:
- case X86::TRUNC_16to8:
- case X86::TRUNC_32_to8:
- case X86::TRUNC_16_to8: {
- const MachineOperand &MO0 = MI->getOperand(0);
- const MachineOperand &MO1 = MI->getOperand(1);
- unsigned Reg0 = MO0.getReg();
- unsigned Reg1 = MO1.getReg();
- unsigned Opc = MI->getOpcode();
- if (Opc == X86::TRUNC_64to32)
- Reg1 = getX86SubSuperRegister(Reg1, MVT::i32);
- else if (Opc == X86::TRUNC_32to16 || Opc == X86::TRUNC_64to16)
- Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
- else
- Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
- O << TAI->getCommentString() << " TRUNCATE ";
- if (Reg0 != Reg1)
- O << "\n\t";
- break;
- }
case X86::PsMOVZX64rr32:
O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
break;