MC: Provide the target triple to AsmBackend constructors.

[oota-llvm.git] / lib / Target / X86 / X86.h

diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 81c68da58e9b1e5cd522828e3165826db29dffa3..c753cf2a530f98c0c3e91fc01301b7986375777f 100644 (file)
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -1,5 +1,12 @@
 //===-- X86.h - Top-level interface for X86 representation ------*- C++ -*-===//
 //
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
 // This file contains the entry points for global functions defined in the x86
 // target library, as used by the LLVM JIT.
 //
@@ -8,57 +15,67 @@
 #ifndef TARGET_X86_H
 #define TARGET_X86_H
 
-#include <iosfwd>
-class TargetMachine;
-class Pass;
+#include "llvm/Target/TargetMachine.h"
 
-/// createSimpleX86InstructionSelector - This pass converts an LLVM function
-/// into a machine code representation is a very simple peep-hole fashion.  The
-/// generated code sucks but the implementation is nice and simple.
-///
-Pass *createSimpleX86InstructionSelector(TargetMachine &TM);
+namespace llvm {
+
+class FunctionPass;
+class JITCodeEmitter;
+class MCCodeEmitter;
+class MCContext;
+class MachineCodeEmitter;
+class Target;
+class TargetAsmBackend;
+class X86TargetMachine;
+class formatted_raw_ostream;
 
-/// createX86PeepholeOptimizer - Create a pass to perform X86 specific peephole
-/// optimizations.
+/// createX86ISelDag - This pass converts a legalized DAG into a 
+/// X86-specific DAG, ready for instruction scheduling.
 ///
-Pass *createX86PeepholeOptimizerPass();
+FunctionPass *createX86ISelDag(X86TargetMachine &TM,
+                               CodeGenOpt::Level OptLevel);
 
 /// createX86FloatingPointStackifierPass - This function returns a pass which
 /// converts floating point register references and pseudo instructions into
 /// floating point stack references and physical instructions.
 ///
-Pass *createX86FloatingPointStackifierPass();
+FunctionPass *createX86FloatingPointStackifierPass();
 
-/// createX86CodePrinterPass - Returns a pass that prints the X86
-/// assembly code for a MachineFunction to the given output stream,
-/// using the given target machine description.  This should work
-/// regardless of whether the function is in SSA form.
+/// createX87FPRegKillInserterPass - This function returns a pass which
+/// inserts FP_REG_KILL instructions where needed.
 ///
-Pass *createX86CodePrinterPass(std::ostream &o, TargetMachine &tm);
+FunctionPass *createX87FPRegKillInserterPass();
 
-/// X86EmitCodeToMemory - This function converts a register allocated function
-/// into raw machine code in a dynamically allocated chunk of memory.  A pointer
-/// to the start of the function is returned.
-///
-Pass *createEmitX86CodeToMemory();
+/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
+/// to the specified MCE object.
+FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM,
+                                          JITCodeEmitter &JCE);
+
+MCCodeEmitter *createX86_32MCCodeEmitter(const Target &, TargetMachine &TM,
+                                         MCContext &Ctx);
+MCCodeEmitter *createX86_64MCCodeEmitter(const Target &, TargetMachine &TM,
+                                         MCContext &Ctx);
 
-/// X86 namespace - This namespace contains all of the register and opcode enums
-/// used by the X86 backend.
+TargetAsmBackend *createX86_32AsmBackend(const Target &, const std::string &);
+TargetAsmBackend *createX86_64AsmBackend(const Target &, const std::string &);
+
+/// createX86EmitCodeToMemory - Returns a pass that converts a register
+/// allocated function into raw machine code in a dynamically
+/// allocated chunk of memory.
 ///
-namespace X86 {
-  // Defines a large number of symbolic names for X86 registers.  This defines a
-  // mapping from register name to register number.
-  //
-  enum Register {
-#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) ENUM,
-#include "X86RegisterInfo.def"
-  };
-
-  // This defines a large number of symbolic names for X86 instruction opcodes.
-  enum Opcode {
-#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) ENUM,
-#include "X86InstrInfo.def"
-  };
-}
+FunctionPass *createEmitX86CodeToMemory();
+
+extern Target TheX86_32Target, TheX86_64Target;
+
+} // End llvm namespace
+
+// Defines symbolic names for X86 registers.  This defines a mapping from
+// register name to register number.
+//
+#include "X86GenRegisterNames.inc"
+
+// Defines symbolic names for the X86 instructions.
+//
+#include "X86GenInstrNames.inc"
 
 #endif