// Random ideas for the X86 backend.
//===---------------------------------------------------------------------===//
-We should add support for the "movbe" instruction, which does a byte-swapping
-copy (3-addr bswap + memory support?) This is available on Atom processors.
-
-//===---------------------------------------------------------------------===//
-
-This should be one DIV/IDIV instruction, not a libcall:
-
-unsigned test(unsigned long long X, unsigned Y) {
- return X/Y;
-}
-
-This can be done trivially with a custom legalizer. What about overflow
-though? http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14224
-
-//===---------------------------------------------------------------------===//
-
Improvements to the multiply -> shift/add algorithm:
http://gcc.gnu.org/ml/gcc-patches/2004-08/msg01590.html
Some isel ideas:
-1. Dynamic programming based approach when compile time if not an
+1. Dynamic programming based approach when compile time is not an
issue.
2. Code duplication (addressing mode) during isel.
3. Other ideas from "Register-Sensitive Selection, Duplication, and
//===---------------------------------------------------------------------===//
-This:
-
-void foo(void);
-void bar(int x, int *P) {
- x >>= 2;
- if (x)
- foo();
- *P = x;
-}
-
-compiles into:
-
- movq %rsi, %rbx
- movl %edi, %r14d
- sarl $2, %r14d
- testl %r14d, %r14d
- je LBB0_2
-
-Instead of doing an explicit test, we can use the flags off the sar. This
-occurs in a bigger testcase like this, which is pretty common:
-
-#include <vector>
-int test1(std::vector<int> &X) {
- int Sum = 0;
- for (long i = 0, e = X.size(); i != e; ++i)
- X[i] = 0;
- return Sum;
-}
-
-//===---------------------------------------------------------------------===//
-
-Only use inc/neg/not instructions on processors where they are faster than
-add/sub/xor. They are slower on the P4 due to only updating some processor
-flags.
-
-//===---------------------------------------------------------------------===//
-
The instruction selector sometimes misses folding a load into a compare. The
pattern is written as (cmp reg, (load p)). Because the compare isn't
commutative, it is not matched with the load on both sides. The dag combiner
-should be made smart enough to cannonicalize the load into the RHS of a compare
+should be made smart enough to canonicalize the load into the RHS of a compare
when it can invert the result of the compare for free.
//===---------------------------------------------------------------------===//
//===---------------------------------------------------------------------===//
-__builtin_ffs codegen is messy.
-
-int ffs_(unsigned X) { return __builtin_ffs(X); }
-
-llvm produces:
-ffs_:
- movl 4(%esp), %ecx
- bsfl %ecx, %eax
- movl $32, %edx
- cmove %edx, %eax
- incl %eax
- xorl %edx, %edx
- testl %ecx, %ecx
- cmove %edx, %eax
- ret
-
-vs gcc:
-
-_ffs_:
- movl $-1, %edx
- bsfl 4(%esp), %eax
- cmove %edx, %eax
- addl $1, %eax
- ret
-
-Another example of __builtin_ffs (use predsimplify to eliminate a select):
-
-int foo (unsigned long j) {
- if (j)
- return __builtin_ffs (j) - 1;
- else
- return 0;
-}
-
-//===---------------------------------------------------------------------===//
-
It appears gcc place string data with linkonce linkage in
.section __TEXT,__const_coal,coalesced instead of
.section __DATA,__const_coal,coalesced.
//===---------------------------------------------------------------------===//
-Use the FLAGS values from arithmetic instructions more. For example, compile:
-
-int add_zf(int *x, int y, int a, int b) {
- if ((*x += y) == 0)
- return a;
- else
- return b;
-}
-
-to:
- addl %esi, (%rdi)
- movl %edx, %eax
- cmovne %ecx, %eax
- ret
-instead of:
-
-_add_zf:
- addl (%rdi), %esi
- movl %esi, (%rdi)
- testl %esi, %esi
- cmove %edx, %ecx
- movl %ecx, %eax
- ret
-
-As another example, compile function f2 in test/CodeGen/X86/cmp-test.ll
-without a test instruction.
-
-//===---------------------------------------------------------------------===//
-
-These two functions have identical effects:
-
-unsigned int f(unsigned int i, unsigned int n) {++i; if (i == n) ++i; return i;}
-unsigned int f2(unsigned int i, unsigned int n) {++i; i += i == n; return i;}
-
-We currently compile them to:
-
-_f:
- movl 4(%esp), %eax
- movl %eax, %ecx
- incl %ecx
- movl 8(%esp), %edx
- cmpl %edx, %ecx
- jne LBB1_2 #UnifiedReturnBlock
-LBB1_1: #cond_true
- addl $2, %eax
- ret
-LBB1_2: #UnifiedReturnBlock
- movl %ecx, %eax
- ret
-_f2:
- movl 4(%esp), %eax
- movl %eax, %ecx
- incl %ecx
- cmpl 8(%esp), %ecx
- sete %cl
- movzbl %cl, %ecx
- leal 1(%ecx,%eax), %eax
- ret
-
-both of which are inferior to GCC's:
-
-_f:
- movl 4(%esp), %edx
- leal 1(%edx), %eax
- addl $2, %edx
- cmpl 8(%esp), %eax
- cmove %edx, %eax
- ret
-_f2:
- movl 4(%esp), %eax
- addl $1, %eax
- xorl %edx, %edx
- cmpl 8(%esp), %eax
- sete %dl
- addl %edx, %eax
- ret
-
-//===---------------------------------------------------------------------===//
-
This code:
void test(int X) {
Take the following:
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-S128"
target triple = "i386-apple-darwin8"
@in_exit.4870.b = internal global i1 false ; <i1*> [#uses=2]
define fastcc void @abort_gzip() noreturn nounwind {
//===---------------------------------------------------------------------===//
-These should compile to the same code, but the later codegen's to useless
-instructions on X86. This may be a trivial dag combine (GCC PR7061):
-
-struct s1 { unsigned char a, b; };
-unsigned long f1(struct s1 x) {
- return x.a + x.b;
-}
-struct s2 { unsigned a: 8, b: 8; };
-unsigned long f2(struct s2 x) {
- return x.a + x.b;
-}
-
-//===---------------------------------------------------------------------===//
-
We currently compile this:
define i32 @func1(i32 %v1, i32 %v2) nounwind {
//===---------------------------------------------------------------------===//
-This code:
-
-void vec_mpys1(int y[], const int x[], int scaler) {
-int i;
-for (i = 0; i < 150; i++)
- y[i] += (((long long)scaler * (long long)x[i]) >> 31);
-}
-
-Compiles to this loop with GCC 3.x:
-
-.L5:
- movl %ebx, %eax
- imull (%edi,%ecx,4)
- shrdl $31, %edx, %eax
- addl %eax, (%esi,%ecx,4)
- incl %ecx
- cmpl $149, %ecx
- jle .L5
-
-llvm-gcc compiles it to the much uglier:
-
-LBB1_1: ## bb1
- movl 24(%esp), %eax
- movl (%eax,%edi,4), %ebx
- movl %ebx, %ebp
- imull %esi, %ebp
- movl %ebx, %eax
- mull %ecx
- addl %ebp, %edx
- sarl $31, %ebx
- imull %ecx, %ebx
- addl %edx, %ebx
- shldl $1, %eax, %ebx
- movl 20(%esp), %eax
- addl %ebx, (%eax,%edi,4)
- incl %edi
- cmpl $150, %edi
- jne LBB1_1 ## bb1
-
-The issue is that we hoist the cast of "scaler" to long long outside of the
-loop, the value comes into the loop as two values, and
-RegsForValue::getCopyFromRegs doesn't know how to put an AssertSext on the
-constructed BUILD_PAIR which represents the cast value.
-
-This can be handled by making CodeGenPrepare sink the cast.
-
-//===---------------------------------------------------------------------===//
-
Test instructions can be eliminated by using EFLAGS values from arithmetic
instructions. This is currently not done for mul, and, or, xor, neg, shl,
sra, srl, shld, shrd, atomic ops, and others. It is also currently not done
The second one is done for: Atom, Pentium Pro, all AMDs, Pentium 4, Nocona,
Core 2, and "Generic"
-//===---------------------------------------------------------------------===//
-
-Testcase:
-int a(int x) { return (x & 127) > 31; }
-
-Current output:
- movl 4(%esp), %eax
- andl $127, %eax
- cmpl $31, %eax
- seta %al
- movzbl %al, %eax
- ret
-
-Ideal output:
- xorl %eax, %eax
- testl $96, 4(%esp)
- setne %al
- ret
-
-This should definitely be done in instcombine, canonicalizing the range
-condition into a != condition. We get this IR:
-
-define i32 @a(i32 %x) nounwind readnone {
-entry:
- %0 = and i32 %x, 127 ; <i32> [#uses=1]
- %1 = icmp ugt i32 %0, 31 ; <i1> [#uses=1]
- %2 = zext i1 %1 to i32 ; <i32> [#uses=1]
- ret i32 %2
-}
-
-Instcombine prefers to strength reduce relational comparisons to equality
-comparisons when possible, this should be another case of that. This could
-be handled pretty easily in InstCombiner::visitICmpInstWithInstAndIntCst, but it
-looks like InstCombiner::visitICmpInstWithInstAndIntCst should really already
-be redesigned to use ComputeMaskedBits and friends.
-
-
//===---------------------------------------------------------------------===//
Testcase:
int x(int a) { return (a&0xf0)>>4; }
//===---------------------------------------------------------------------===//
-Take the following C code:
-int x(int y) { return (y & 63) << 14; }
-
-Code produced by gcc:
- andl $63, %edi
- sall $14, %edi
- movl %edi, %eax
- ret
-
-Code produced by clang:
- shll $14, %edi
- movl %edi, %eax
- andl $1032192, %eax
- ret
-
-The code produced by gcc is 3 bytes shorter. This sort of construct often
-shows up with bitfields.
-
-//===---------------------------------------------------------------------===//
-
Take the following C code:
int f(int a, int b) { return (unsigned char)a == (unsigned char)b; }
The move of 0 could be scheduled above the test to make it is xor reg,reg.
//===---------------------------------------------------------------------===//
+
+GCC PR48986. We currently compile this:
+
+void bar(void);
+void yyy(int* p) {
+ if (__sync_fetch_and_add(p, -1) == 1)
+ bar();
+}
+
+into:
+ movl $-1, %eax
+ lock
+ xaddl %eax, (%rdi)
+ cmpl $1, %eax
+ je LBB0_2
+
+Instead we could generate:
+
+ lock
+ dec %rdi
+ je LBB0_2
+
+The trick is to match "fetch_and_add(X, -C) == C".
+
+//===---------------------------------------------------------------------===//
+
+unsigned t(unsigned a, unsigned b) {
+ return a <= b ? 5 : -5;
+}
+
+We generate:
+ movl $5, %ecx
+ cmpl %esi, %edi
+ movl $-5, %eax
+ cmovbel %ecx, %eax
+
+GCC:
+ cmpl %edi, %esi
+ sbbl %eax, %eax
+ andl $-10, %eax
+ addl $5, %eax
+
+//===---------------------------------------------------------------------===//
projects / oota-llvm.git / blobdiff