Clean up code a bit.

[oota-llvm.git] / lib / Target / X86 / InstSelectPattern.cpp

diff --git a/lib/Target/X86/InstSelectPattern.cpp b/lib/Target/X86/InstSelectPattern.cpp
index 4b9e381ec173fadf20d8074727390fb69689b801..6b848b00ea2f8f558d8e371b2910fb43b3620fd0 100644 (file)
--- a/lib/Target/X86/InstSelectPattern.cpp
+++ b/lib/Target/X86/InstSelectPattern.cpp
@@ -1,4 +1,11 @@
 //===-- InstSelectPattern.cpp - A pattern matching inst selector for X86 --===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
 //
 // This file defines a pattern matching instruction selector for X86.
 //
@@ -20,12 +27,7 @@
 
 // Include the generated instruction selector...
 #include "X86GenInstrSelector.inc"
-
-
-//===----------------------------------------------------------------------===//
-//  User code
-//
-
+using namespace llvm;
 
 namespace {
   struct ISel : public FunctionPass, SelectionDAGTargetBuilder {
@@ -49,12 +51,14 @@ namespace {
   public:  // Implementation of the SelectionDAGTargetBuilder class...
     /// expandArguments - Add nodes to the DAG to indicate how to load arguments
     /// off of the X86 stack.
-    void expandArguments(SelectionDAG &SD, MachineFunction &MF);
+    void expandArguments(SelectionDAG &SD);
+    void expandCall(SelectionDAG &SD, CallInst &CI);
   };
 }
 
 
-void ISel::expandArguments(SelectionDAG &SD, MachineFunction &F) {
+void ISel::expandArguments(SelectionDAG &SD) {
+
   // Add DAG nodes to load the arguments...  On entry to a function on the X86,
   // the stack frame looks like this:
   //
@@ -63,10 +67,11 @@ void ISel::expandArguments(SelectionDAG &SD, MachineFunction &F) {
   // [ESP + 8] -- second argument, if first argument is four bytes in size
   //    ... 
   //
-  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
+  MachineFunction &F = SD.getMachineFunction();
   MachineFrameInfo *MFI = F.getFrameInfo();
   const Function &Fn = *F.getFunction();
   
+  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
   for (Function::const_aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
     MVT::ValueType ObjectVT = SD.getValueType(I->getType());
     unsigned ArgIncrement = 4;
@@ -84,7 +89,6 @@ void ISel::expandArguments(SelectionDAG &SD, MachineFunction &F) {
     int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
     
     // Create the SelectionDAG nodes corresponding to a load from this parameter
-    // FIXME:
     SelectionDAGNode *FIN = new SelectionDAGNode(ISD::FrameIndex, MVT::i32);
     FIN->addValue(new ReducedValue_FrameIndex_i32(FI));
 
@@ -107,11 +111,14 @@ void ISel::expandArguments(SelectionDAG &SD, MachineFunction &F) {
     VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
 }
 
+void ISel::expandCall(SelectionDAG &SD, CallInst &CI) {
+  assert(0 && "ISel::expandCall not implemented!");
+}
 
 /// createX86PatternInstructionSelector - This pass converts an LLVM function
 /// into a machine code representation using pattern matching and a machine
 /// description file.
 ///
-Pass *createX86PatternInstructionSelector(TargetMachine &TM) {
+FunctionPass *llvm::createX86PatternInstructionSelector(TargetMachine &TM) {
   return new ISel(TM);  
 }