}
def set;
+def implicit;
+def parallel;
def node;
def srcvalue;
SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
+
+def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
+ SDTypeProfile<1, 2, []>>;
+def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
+ SDTypeProfile<1, 3, []>>;
// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
// these internally. Don't reference these directly.
LD->getLoadedVT() == MVT::f32;
return false;
}]>;
+def extloadf64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
+ if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
+ return LD->getExtensionType() == ISD::EXTLOAD &&
+ LD->getAddressingMode() == ISD::UNINDEXED &&
+ LD->getLoadedVT() == MVT::f64;
+ return false;
+}]>;
def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
ST->getAddressingMode() == ISD::UNINDEXED;
return false;
}]>;
+def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
+ (st node:$val, node:$ptr), [{
+ if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
+ return ST->isTruncatingStore() && ST->getStoredVT() == MVT::f64 &&
+ ST->getAddressingMode() == ISD::UNINDEXED;
+ return false;
+}]>;
// indexed store fragments.
def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),