-//===-- TargetMachine.cpp - General Target Information ---------------------==//
+//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
//
-// This file describes the general parts of a Target machine.
-// This file also implements MachineInstrInfo and MachineCacheInfo.
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file implements the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetAsmInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
+using namespace llvm;
-#include "llvm/Target/MachineInstrInfo.h"
-#include "llvm/Constant.h"
-#include "llvm/DerivedTypes.h"
+//===----------------------------------------------------------------------===//
+// TargetOperandInfo
+//===----------------------------------------------------------------------===//
+
+/// getRegClass - Get the register class for the operand, handling resolution
+/// of "symbolic" pointer register classes etc. If this is not a register
+/// operand, this returns null.
+const TargetRegisterClass *
+TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
+ if (isLookupPtrRegClass())
+ return TRI->getPointerRegClass(RegClass);
+ return TRI->getRegClass(RegClass);
+}
-//---------------------------------------------------------------------------
-// class MachineInstructionInfo
-// Interface to description of machine instructions
-//---------------------------------------------------------------------------
+//===----------------------------------------------------------------------===//
+// TargetInstrInfo
+//===----------------------------------------------------------------------===//
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
+ unsigned numOpcodes)
+ : Descriptors(Desc), NumOpcodes(numOpcodes) {
+}
-MachineInstrInfo::MachineInstrInfo(const MachineInstrDescriptor* Desc,
- unsigned DescSize,
- unsigned NumRealOpCodes)
- : desc(Desc), descSize(DescSize), numRealOpCodes(NumRealOpCodes) {
- // FIXME: TargetInstrDescriptors should not be global
- assert(TargetInstrDescriptors == NULL && desc != NULL);
- TargetInstrDescriptors = desc; // initialize global variable
+TargetInstrInfo::~TargetInstrInfo() {
}
-MachineInstrInfo::~MachineInstrInfo() {
- TargetInstrDescriptors = NULL; // reset global variable
+/// insertNoop - Insert a noop into the instruction stream at the specified
+/// point.
+void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
+ llvm_unreachable("Target didn't implement insertNoop!");
}
-bool MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
- int64_t intValue) const {
- // First, check if opCode has an immed field.
- bool isSignExtended;
- uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
- if (maxImmedValue != 0)
- {
- // NEED TO HANDLE UNSIGNED VALUES SINCE THEY MAY BECOME MUCH
- // SMALLER AFTER CASTING TO SIGN-EXTENDED int, short, or char.
- // See CreateUIntSetInstruction in SparcInstrInfo.cpp.
-
- // Now check if the constant fits
- if (intValue <= (int64_t) maxImmedValue &&
- intValue >= -((int64_t) maxImmedValue+1))
- return true;
- }
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.isTerminator()) return false;
- return false;
+ // Conditional branch is a special case.
+ if (TID.isBranch() && !TID.isBarrier())
+ return true;
+ if (!TID.isPredicable())
+ return true;
+ return !isPredicated(MI);
}
-bool MachineInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const {
- assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType()));
- return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType()));
+
+/// Measure the specified inline asm to determine an approximation of its
+/// length.
+/// Comments (which run till the next SeparatorChar or newline) do not
+/// count as an instruction.
+/// Any other non-whitespace text is considered an instruction, with
+/// multiple instructions separated by SeparatorChar or newlines.
+/// Variable-length instructions are not handled here; this function
+/// may be overloaded in the target code to do that.
+unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
+ const TargetAsmInfo &TAI) const {
+
+
+ // Count the number of instructions in the asm.
+ bool atInsnStart = true;
+ unsigned Length = 0;
+ for (; *Str; ++Str) {
+ if (*Str == '\n' || *Str == TAI.getSeparatorChar())
+ atInsnStart = true;
+ if (atInsnStart && !isspace(*Str)) {
+ Length += TAI.getMaxInstLength();
+ atInsnStart = false;
+ }
+ if (atInsnStart && strncmp(Str, TAI.getCommentString(),
+ strlen(TAI.getCommentString())) == 0)
+ atInsnStart = false;
+ }
+
+ return Length;
}