-//===-- TargetMachine.cpp - General Target Information ---------------------==//
+//===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
//
-// This file describes the general parts of a Target machine.
-// This file also implements MachineInstrInfo and MachineCacheInfo.
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Constant.h"
#include "llvm/DerivedTypes.h"
+using namespace llvm;
+
+/// findTiedToSrcOperand - Returns the operand that is tied to the specified
+/// dest operand. Returns -1 if there isn't one.
+int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
+ for (unsigned i = 0, e = numOperands; i != e; ++i) {
+ if (i == OpNum)
+ continue;
+ if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)
+ return i;
+ }
+ return -1;
+}
+
-// External object describing the machine instructions
-// Initialized only when the TargetMachine class is created
-// and reset when that class is destroyed.
-//
-const MachineInstrDescriptor* TargetInstrDescriptors = 0;
-
-//---------------------------------------------------------------------------
-// class MachineInstructionInfo
-// Interface to description of machine instructions
-//---------------------------------------------------------------------------
-
-
-MachineInstrInfo::MachineInstrInfo(const MachineInstrDescriptor* Desc,
- unsigned DescSize,
- unsigned NumRealOpCodes)
- : desc(Desc), descSize(DescSize), numRealOpCodes(NumRealOpCodes) {
- // FIXME: TargetInstrDescriptors should not be global
- assert(TargetInstrDescriptors == NULL && desc != NULL);
- TargetInstrDescriptors = desc; // initialize global variable
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
+ unsigned numOpcodes)
+ : desc(Desc), NumOpcodes(numOpcodes) {
}
-MachineInstrInfo::~MachineInstrInfo() {
- TargetInstrDescriptors = NULL; // reset global variable
+TargetInstrInfo::~TargetInstrInfo() {
}
+// commuteInstruction - The default implementation of this method just exchanges
+// operand 1 and 2.
+MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
+ assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
+ "This only knows how to commute register operands so far");
+ unsigned Reg1 = MI->getOperand(1).getReg();
+ unsigned Reg2 = MI->getOperand(2).getReg();
+ bool Reg1IsKill = MI->getOperand(1).isKill();
+ bool Reg2IsKill = MI->getOperand(2).isKill();
+ MI->getOperand(2).setReg(Reg1);
+ MI->getOperand(1).setReg(Reg2);
+ if (Reg1IsKill)
+ MI->getOperand(2).setIsKill();
+ else
+ MI->getOperand(2).unsetIsKill();
+ if (Reg2IsKill)
+ MI->getOperand(1).setIsKill();
+ else
+ MI->getOperand(1).unsetIsKill();
+ return MI;
+}
-bool MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
- int64_t intValue) const {
- // First, check if opCode has an immed field.
- bool isSignExtended;
- uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
- if (maxImmedValue != 0)
- {
- // NEED TO HANDLE UNSIGNED VALUES SINCE THEY MAY BECOME MUCH
- // SMALLER AFTER CASTING TO SIGN-EXTENDED int, short, or char.
- // See CreateUIntSetInstruction in SparcInstrInfo.cpp.
-
- // Now check if the constant fits
- if (intValue <= (int64_t) maxImmedValue &&
- intValue >= -((int64_t) maxImmedValue+1))
- return true;
+bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
+ const std::vector<MachineOperand> &Pred) const {
+ bool MadeChange = false;
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ if (TID->Flags & M_PREDICABLE) {
+ for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg()) {
+ MO.setReg(Pred[j].getReg());
+ MadeChange = true;
+ } else if (MO.isImm()) {
+ MO.setImm(Pred[j].getImmedValue());
+ MadeChange = true;
+ } else if (MO.isMBB()) {
+ MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
+ MadeChange = true;
+ }
+ ++j;
+ }
}
-
- return false;
+ }
+ return MadeChange;
}
-bool MachineInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const {
- assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType()));
- return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType()));
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ if (TID->Flags & M_TERMINATOR_FLAG) {
+ // Conditional branch is a special case.
+ if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
+ return true;
+ if ((TID->Flags & M_PREDICABLE) == 0)
+ return true;
+ return !isPredicated(MI);
+ }
+ return false;
}