Fix the InsertAtEnd form of ShuffleVectorInst constructor to use

[oota-llvm.git] / lib / Target / TargetInstrInfo.cpp

diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index f377d67b66f7606be0ee3c2fb0709ba027756010..094a57edb419adbe773d3b7c814f19760c5d0f5c 100644 (file)
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -1,61 +1,95 @@
 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
 //===----------------------------------------------------------------------===//
 //
+// This file implements the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Constant.h"
-#include "llvm/DerivedTypes.h"
-
-// External object describing the machine instructions
-// Initialized only when the TargetMachine class is created
-// and reset when that class is destroyed.
-// 
-const TargetInstrDescriptor* TargetInstrDescriptors = 0;
-
-
-TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
-                                unsigned DescSize,
-                                unsigned NumRealOpCodes)
-  : desc(Desc), descSize(DescSize), numRealOpCodes(NumRealOpCodes) {
-  // FIXME: TargetInstrDescriptors should not be global
-  assert(TargetInstrDescriptors == NULL && desc != NULL);
-  TargetInstrDescriptors = desc;       // initialize global variable
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Support/ErrorHandling.h"
+using namespace llvm;
+
+//===----------------------------------------------------------------------===//
+//  TargetOperandInfo
+//===----------------------------------------------------------------------===//
+
+/// getRegClass - Get the register class for the operand, handling resolution
+/// of "symbolic" pointer register classes etc.  If this is not a register
+/// operand, this returns null.
+const TargetRegisterClass *
+TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
+  if (isLookupPtrRegClass())
+    return TRI->getPointerRegClass(RegClass);
+  return TRI->getRegClass(RegClass);
+}
+
+//===----------------------------------------------------------------------===//
+//  TargetInstrInfo
+//===----------------------------------------------------------------------===//
+
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
+                                 unsigned numOpcodes)
+  : Descriptors(Desc), NumOpcodes(numOpcodes) {
 }
 
 TargetInstrInfo::~TargetInstrInfo() {
-  TargetInstrDescriptors = NULL;       // reset global variable
 }
 
-bool TargetInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
-                                              int64_t intValue) const {
-  // First, check if opCode has an immed field.
-  bool isSignExtended;
-  uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
-  if (maxImmedValue != 0)
-    {
-      // NEED TO HANDLE UNSIGNED VALUES SINCE THEY MAY BECOME MUCH
-      // SMALLER AFTER CASTING TO SIGN-EXTENDED int, short, or char.
-      // See CreateUIntSetInstruction in SparcInstrInfo.cpp.
-      
-      // Now check if the constant fits
-      if (intValue <= (int64_t) maxImmedValue &&
-         intValue >= -((int64_t) maxImmedValue+1))
-       return true;
-    }
+/// insertNoop - Insert a noop into the instruction stream at the specified
+/// point.
+void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB, 
+                                 MachineBasicBlock::iterator MI) const {
+  llvm_unreachable("Target didn't implement insertNoop!");
+}
+
+
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
+  const TargetInstrDesc &TID = MI->getDesc();
+  if (!TID.isTerminator()) return false;
   
-  return false;
+  // Conditional branch is a special case.
+  if (TID.isBranch() && !TID.isBarrier())
+    return true;
+  if (!TID.isPredicable())
+    return true;
+  return !isPredicated(MI);
 }
 
-bool TargetInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const {
-  assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType()));
-  return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType()));
+
+/// Measure the specified inline asm to determine an approximation of its
+/// length.
+/// Comments (which run till the next SeparatorChar or newline) do not
+/// count as an instruction.
+/// Any other non-whitespace text is considered an instruction, with
+/// multiple instructions separated by SeparatorChar or newlines.
+/// Variable-length instructions are not handled here; this function
+/// may be overloaded in the target code to do that.
+unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
+                                             const MCAsmInfo &MAI) const {
+  
+  
+  // Count the number of instructions in the asm.
+  bool atInsnStart = true;
+  unsigned Length = 0;
+  for (; *Str; ++Str) {
+    if (*Str == '\n' || *Str == MAI.getSeparatorChar())
+      atInsnStart = true;
+    if (atInsnStart && !isspace(*Str)) {
+      Length += MAI.getMaxInstLength();
+      atInsnStart = false;
+    }
+    if (atInsnStart && strncmp(Str, MAI.getCommentString(),
+                               strlen(MAI.getCommentString())) == 0)
+      atInsnStart = false;
+  }
+  
+  return Length;
 }