This is the initial check-in for adding register scavenging to PPC. (Currently,

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 766966f5507078cb62f6b7e8f4262b653214e108..cebac7a263650b8b01f7ea5043b73025fe7a3c74 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -25,6 +25,7 @@ class RegisterClass; // Forward def
 // in the target machine.  String n will become the "name" of the register.
 class Register<string n> {
   string Namespace = "";
+  string AsmName = n;
   string Name = n;
 
   // SpillSize - If this value is set to a non-zero value, it is the size in
@@ -204,19 +205,20 @@ class Instruction {
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
 
-  // Side effect flags - If neither of these flags is set, then the instruction
-  // *always* has side effects. When set, the flags have these meanings:
+  // Side effect flags - When set, the flags have these meanings:
   //
-  //  neverHasSideEffects - The instruction has no side effects that are not
-  //    captured by any operands of the instruction or other flags, and when
-  //    *all* instances of the instruction of that opcode have no side effects.
+  //  hasSideEffects - The instruction has side effects that are not
+  //    captured by any operands of the instruction or other flags.
   //  mayHaveSideEffects  - Some instances of the instruction can have side
   //    effects. The virtual method "isReallySideEffectFree" is called to
   //    determine this. Load instructions are an example of where this is
   //    useful. In general, loads always have side effects. However, loads from
   //    constant pools don't. Individual back ends make this determination.
-  bit neverHasSideEffects = 0;
+  //  neverHasSideEffects - Set on an instruction with no pattern if it has no
+  //    side effects.
+  bit hasSideEffects = 0;
   bit mayHaveSideEffects = 0;
+  bit neverHasSideEffects = 0;
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 
@@ -276,6 +278,9 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+def f32imm : Operand<f32>;
+def f64imm : Operand<f64>;
+
 /// zero_reg definition - Special node to stand for the zero register.
 ///
 def zero_reg;
@@ -333,22 +338,31 @@ def INLINEASM : Instruction {
 }
 def LABEL : Instruction {
   let OutOperandList = (ops);
-  let InOperandList = (ops i32imm:$id);
+  let InOperandList = (ops i32imm:$id, i32imm:$flavor);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+  let hasCtrlDep = 1;
+}
+def DECLARE : Instruction {
+  let OutOperandList = (ops);
+  let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
   let hasCtrlDep = 1;
 }
 def EXTRACT_SUBREG : Instruction {
-        let OutOperandList = (ops variable_ops);
+  let OutOperandList = (ops variable_ops);
   let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
+  let neverHasSideEffects = 1;
 }
 def INSERT_SUBREG : Instruction {
         let OutOperandList = (ops variable_ops);
   let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
+  let neverHasSideEffects = 1;
 }
 
 //===----------------------------------------------------------------------===//