//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// in the target machine. String n will become the "name" of the register.
class Register<string n> {
string Namespace = "";
+ string AsmName = n;
string Name = n;
// SpillSize - If this value is set to a non-zero value, it is the size in
// Aliases - A list of registers that this register overlaps with. A read or
// modification of this register can potentially read or modify the aliased
// registers.
- //
list<Register> Aliases = [];
- // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+ // SubRegs - A list of registers that are parts of this register. Note these
+ // are "immediate" sub-registers and the registers within the list do not
+ // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
+ // not [AX, AH, AL].
+ list<Register> SubRegs = [];
+
+ // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
// These values can be determined by locating the <target>.h file in the
// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
// order of these names correspond to the enumeration used by gcc. A value of
- // -1 indicates that the gcc number is undefined.
- int DwarfNumber = -1;
+ // -1 indicates that the gcc number is undefined and -2 that register number
+ // is invalid for this mode/flavour.
+ list<int> DwarfNumbers = [];
}
-// RegisterGroup - This can be used to define instances of Register which
-// need to specify aliases.
-// List "aliases" specifies which registers are aliased to this one. This
-// allows the code generator to be careful not to put two values with
+// RegisterWithSubRegs - This can be used to define instances of Register which
+// need to specify sub-registers.
+// List "subregs" specifies which registers are sub-registers to this one. This
+// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
+// This allows the code generator to be careful not to put two values with
// overlapping live ranges into registers which alias.
-class RegisterGroup<string n, list<Register> aliases> : Register<n> {
- let Aliases = aliases;
+class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
+ let SubRegs = subregs;
+}
+
+// SubRegSet - This can be used to define a specific mapping of registers to
+// indices, for use as named subregs of a particular physical register. Each
+// register in 'subregs' becomes an addressable subregister at index 'n' of the
+// corresponding register in 'regs'.
+class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
+ int index = n;
+
+ list<Register> From = regs;
+ list<Register> To = subregs;
}
// RegisterClass - Now that all of the registers are defined, and aliases
//
int Alignment = alignment;
+ // CopyCost - This value is used to specify the cost of copying a value
+ // between two registers in this register class. The default value is one
+ // meaning it takes a single instruction to perform the copying. A negative
+ // value means copying is extremely expensive or impossible.
+ int CopyCost = 1;
+
// MemberList - Specify which registers are in this class. If the
// allocation_order_* method are not specified, this also defines the order of
// allocation used by the register allocator.
//
list<Register> MemberList = regList;
+
+ // SubClassList - Specify which register classes correspond to subregisters
+ // of this class. The order should be by subregister set index.
+ list<RegisterClass> SubRegClassList = [];
// MethodProtos/MethodBodies - These members can be used to insert arbitrary
// code into a generated register class. The normal usage of this is to
// to the register numbering used by gcc and gdb. These values are used by a
// debug information writer (ex. DwarfWriter) to describe where values may be
// located during execution.
-class DwarfRegNum<int N> {
- // DwarfNumber - Number used internally by gcc/gdb to identify the register.
+class DwarfRegNum<list<int> Numbers> {
+ // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
// These values can be determined by locating the <target>.h file in the
// directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
// order of these names correspond to the enumeration used by gcc. A value of
- // -1 indicates that the gcc number is undefined.
- int DwarfNumber = N;
+ // -1 indicates that the gcc number is undefined and -2 that register number is
+ // invalid for this mode/flavour.
+ list<int> DwarfNumbers = Numbers;
}
//===----------------------------------------------------------------------===//
// the Target/TargetInstrInfo.h file.
//
class Instruction {
- string Name = ""; // The opcode string for this instruction
string Namespace = "";
- dag OperandList; // An dag containing the MI operand list.
+ dag OutOperandList; // An dag containing the MI def operand list.
+ dag InOperandList; // An dag containing the MI use operand list.
string AsmString = ""; // The .s format to print the instruction with.
// Pattern - Set to the DAG pattern for this instruction, if we know of one,
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
+ bit isIndirectBranch = 0; // Is this instruction an indirect branch?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
- bit isLoad = 0; // Is this instruction a load instruction?
- bit isStore = 0; // Is this instruction a store instruction?
+ bit isSimpleLoad = 0; // Is this just a load instruction?
+ bit mayLoad = 0; // Is it possible for this inst to read memory?
+ bit mayStore = 0; // Is it possible for this inst to write memory?
+ bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
+ bit isReMaterializable = 0; // Is this instruction re-materializable?
+ bit isPredicable = 0; // Is this instruction predicable?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
- bit noResults = 0; // Does this instruction produce no results?
+ bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
+
+ // Side effect flags - When set, the flags have these meanings:
+ //
+ // hasSideEffects - The instruction has side effects that are not
+ // captured by any operands of the instruction or other flags.
+ // mayHaveSideEffects - Some instances of the instruction can have side
+ // effects. The virtual method "isReallySideEffectFree" is called to
+ // determine this. Load instructions are an example of where this is
+ // useful. In general, loads always have side effects. However, loads from
+ // constant pools don't. Individual back ends make this determination.
+ // neverHasSideEffects - Set on an instruction with no pattern if it has no
+ // side effects.
+ bit hasSideEffects = 0;
+ bit mayHaveSideEffects = 0;
+ bit neverHasSideEffects = 0;
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
string DisableEncoding = "";
}
-/// Imp - Helper class for specifying the implicit uses/defs set for an
-/// instruction.
-class Imp<list<Register> uses, list<Register> defs> {
- list<Register> Uses = uses;
- list<Register> Defs = defs;
-}
-
/// Predicates - These are extra conditionals which are turned into instruction
/// selector matching code. Currently each predicate is just a string.
class Predicate<string cond> {
string CondString = cond;
}
+/// NoHonorSignDependentRounding - This predicate is true if support for
+/// sign-dependent-rounding is not enabled.
+def NoHonorSignDependentRounding
+ : Predicate<"!HonorSignDependentRoundingFPMath()">;
+
class Requires<list<Predicate> preds> {
list<Predicate> Predicates = preds;
}
/// ops definition - This is just a simple marker used to identify the operands
-/// list for an instruction. This should be used like this:
-/// (ops R32:$dst, R32:$src) or something similar.
+/// list for an instruction. outs and ins are identical both syntatically and
+/// semantically, they are used to define def operands and use operands to
+/// improve readibility. This should be used like this:
+/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
def ops;
+def outs;
+def ins;
/// variable_ops definition - Mark this instruction as taking a variable number
/// of operands.
def i32imm : Operand<i32>;
def i64imm : Operand<i64>;
+def f32imm : Operand<f32>;
+def f64imm : Operand<f64>;
+
+/// zero_reg definition - Special node to stand for the zero register.
+///
+def zero_reg;
/// PredicateOperand - This can be used to define a predicate operand for an
/// instruction. OpTypes specifies the MIOperandInfo for the operand, and
/// AlwaysVal specifies the value of this predicate when set to "always
/// execute".
-class PredicateOperand<dag OpTypes, dag AlwaysVal> : Operand<OtherVT> {
+class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
+ : Operand<ty> {
+ let MIOperandInfo = OpTypes;
+ dag DefaultOps = AlwaysVal;
+}
+
+/// OptionalDefOperand - This is used to define a optional definition operand
+/// for an instruction. DefaultOps is the register the operand represents if none
+/// is supplied, e.g. zero_reg.
+class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
+ : Operand<ty> {
let MIOperandInfo = OpTypes;
- dag ExecuteAlways = AlwaysVal;
+ dag DefaultOps = defaultops;
}
// Standard Instructions.
def PHI : Instruction {
- let OperandList = (ops variable_ops);
+ let OutOperandList = (ops);
+ let InOperandList = (ops variable_ops);
let AsmString = "PHINODE";
let Namespace = "TargetInstrInfo";
}
def INLINEASM : Instruction {
- let OperandList = (ops variable_ops);
+ let OutOperandList = (ops);
+ let InOperandList = (ops variable_ops);
let AsmString = "";
let Namespace = "TargetInstrInfo";
}
def LABEL : Instruction {
- let OperandList = (ops i32imm:$id);
+ let OutOperandList = (ops);
+ let InOperandList = (ops i32imm:$id, i32imm:$flavor);
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
}
+def DECLARE : Instruction {
+ let OutOperandList = (ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let hasCtrlDep = 1;
+}
+def EXTRACT_SUBREG : Instruction {
+ let OutOperandList = (ops variable_ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let neverHasSideEffects = 1;
+}
+def INSERT_SUBREG : Instruction {
+ let OutOperandList = (ops variable_ops);
+ let InOperandList = (ops variable_ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let neverHasSideEffects = 1;
+}
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize
//===----------------------------------------------------------------------===//
// SubtargetFeature - A characteristic of the chip set.
//
-class SubtargetFeature<string n, string a, string v, string d> {
+class SubtargetFeature<string n, string a, string v, string d,
+ list<SubtargetFeature> i = []> {
// Name - Feature name. Used by command line (-mattr=) to determine the
// appropriate target chip.
//
// information.
//
string Desc = d;
+
+ // Implies - Features that this feature implies are present. If one of those
+ // features isn't set, then this one shouldn't be set either.
+ //
+ list<SubtargetFeature> Implies = i;
}
//===----------------------------------------------------------------------===//
}
//===----------------------------------------------------------------------===//
-// Pull in the common support for DAG isel generation
+// Pull in the common support for calling conventions.
+//
+include "TargetCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for DAG isel generation.
//
include "TargetSelectionDAG.td"
projects / oota-llvm.git / blobdiff